bcd adder experiment

Observe that only 10 of the 16 possible bit-patterns are used in BCD.   That means the remaining 6 patterns could be treated as don't-care cases. 

For the arithmetic addition of two decimal digits in BCD, the maximum value that may be produced as the result   is 9 + 9 + 1 = 19 (two largest operands plus the carry). If we try to add two decimal digits in BCD with a 4-bit ripple-carry adder we will get a binary sum ranging from 0 to 19. When the binary sum is less than or equal to 9, it also correctly represents the sum in BCD.   When the binary sum is greater than 9, however, it does not represent the correct BCD sum. The sum in BCD is to be obtained by adding 6 to it. 

Perform the following addition in BCD as explained above:

1) 7 + 4  2) 3 + 2  3) 9 + 9 

The above examples should help you realize when the conversion is necessary and what should be done to perform the conversion correctly. 

Here is a block diagram of a 1-digit BCD adder  

Complete the truth table below.   

  Prelab

• Complete the truth table in the Theory section.
• Upon an inspection of the 1-digit BCD adder block diagram shown above, you should notice that the only block you do not have a circuit for is the “ Sum > 9”? block. (MAX+plus II has a prebuilt circuit for a 2x1 Multiplexor called 21mux in the mf symbol library if you need it. Yes, you can build the same BCD adder without using multiplexors, but you will need to explain your circuit in the Circuits Built section of you lab report.) Design the circuit to perform this function. (Hint: Create the truth table and use K-maps to simplify the circuit.) You will need to show your work. Having the circuit just magically appear on your circuit diagrams and saying you got it from the book will not be good enough.

  Procedure

• Using the table and block diagram above, build a 1-digit BCD adder using two 4-bit ripple-carry adders and possibly some other logic gates. Create a folder on your disk and name it Lab5. Copy the 4-bit adder you created in Lab 3 to the Lab4 folder. You will need to copy the following files:
• 4bitadder.sym 
• 4bitadder.gdf 
• fa.gdf 
• ha.gdf 

Make sure that your 1-digit BCD adder gives the correct values. (Verify with your table and resolve any differences by correcting your circuit. Note: you don't have to simulate all the different possibilities, just the ones in the table above.) Save this project as 1digitBCD in the folder Lab4. Create a default symbol for the 1-digit BCD adder for use in the next step.

Note: You can use the gnd symbol to simulate a zero, and the vcc symbol to simulate a one, if necessary.  

• Build a 2-digit BCD adder using two 1-digit BCD adders. Test the 2-digit BCD adder with the following test cases:

o         0 + 0

o         9 + 10

o         99 + 99

o         16 + 64

Save this project as 2digitBCD in the folder Lab4.

  What to turn in

• Completed truth table in the Theory section.
• All work related to the building of the Sum > 9? circuit. (Truth tables, K-maps, Boolean equations, etc., if any.)
• 1digitBCD (.gdf, .scf)
• 2digitBCD (.gdf, .scf)

BCD Adder – Block Diagram, Truth table & Circuit

In this lecture, we are going to learn about the what is BCD adder, the BCD adder circuit diagram, the BCD adder truth table, the BCD adder block diagram, and the operation of the BCD Adder in every detail.

Computers to calculators that carry out the arithmetic operations directly in the decimal number system represent the decimal numbers in the BCD form. In this lecture, we will discuss the BCD Adder in detail and then in the next lecture, we will cover the BCD subtractor circuit.

Table of Contents

What is BCD Adder

• A BCD Adder adds two BCD digits and produces a BCD digit, A BCD cannot be greater than 9.
• The two given BCD numbers are to be added using the rules of binary addition.
• If the sum is less than or equal to 9 and carry = 0, then no correction is necessary. The sum is correct and in the true BCD form.
• But if the sum is invalid BCD or carry = 1, then the result is wrong and needs correction.
• The wrong result can be corrected by adding six (0110) to it.

BCD Adder Block Diagram

From the above point which we have discussed, we understand that the 4 bit BCD adder should consist of the following blocks.

• A 4 bit binary adder to add the given numbers A and B.
• A combinational circuit to check if the sum is greater than 9 or carry = 1.
• One or more 4-bit binary adder to add six (0110) to the incorrect sum if sum > 9 or carry 1.

The block diagram of such a BCD adder is shown in the figure below.

From the above discussed, we can conclude that before getting the knowledge about eh operation of BCD adder, we have to design a combinational circuit that sense if the sum is greater than 9 or carry=1.

Design of Combination circuit of BCD adder

To design any combinational circuit, we have to make a truth table for that combinational circuit, and by using the k-map we have to realize the expression for that logic diagram to build the circuit.

Here, the output of the combinational circuit should be 1 if the sum produced by the adder is greater than 9 i.e. 1001. The truth table is as follows:

BCD Adder Truth Table

From the truth table, we can see that, when the sum is valid BCD numbers then Y = 0, and when the sum is invalid BCD numbers then Y = 1.

So from the above truth table now we are going to make the combinational circuit for the BCD adder so correct the BCD number when the invalid BCD number is getting from the output.

To build the combination circuit now we will use k-map to realize the boolean expression for the combinational circuit.

K-Map for BCD adder combination circuit

The K-map for output Y of the combination circuit of the BCD adder is shown in the figure below:

From the above K-map, we can write the Boolean expression as:

\mathbf{Y = S_3S_2 + S_3S_1}

Also Read: Magnitude Comparator and Digital Comparator

BCD Adder Circuit Diagram

The BCD adder circuit is shown in the below figure.

We can make a BCD adder using ic 7483 as per the below image.

The output of the combinational circuit should be 1 if the Cout of adder-1 is high. therefore Y is ORed with Cout of the adder 1 as shown in the figure.

the output of the combinational circuit is connected to B 1 B 2 inputs of adder-2 and B 3 =B 1 =0 as they are connected to the ground permanently. This makes B 3 B 2 B 1 B 0 = 0 1 1 0 if Y’ = 1.

The sum outputs of adder-1 are applied to A 3 A 2 A 1 A 0 of adder-2. The output of the combinational circuit is to be used as the final output carry and the carry output of adder-2 is to be ignored.

Operation of BCD Adder

So now we are going to see the actual operation of BCD adder and how bcd adder works. For reference please check the above figure while studying the operation of the BCD adder.

Case 1: Sum <= 9 and Carry = 0

• The output of combinational circuit Y’ = 0. Hence B 3 B 2 B 1 B 0 = 0000 for adder-2.
• Hence the output of adder-2 is the same as that of adder-2.

Case 2: Sum > 9 and Carry = 0

• If S 3 S 2 S 1 S 0 of adder-1 is greater than 9, then output Y’ of the combinational circuit becomes 1.
• Therefore B 3 B 2 B 1 B 0 = 0110 (adder-2).
• hence six(0110) will be added to the sum output of adder-1.
• We get the corrected BCD result at the output of adder-2

Case 3: Sum <= 9 and Carry = 1

• As the carry output of adder-1 is high, Y’ = 1.
• Therefore B 3 B 2 B 1 B 0 = 0110 (adder-2)
• So, 0110 will be added to the sum output of adder-1.
• We get the corrected BCD result at the output of adder-2.

Thus, we can make a 4-bit BCD adder using the binary adder.

Also Read: Half Adder in Digital Electronics

8-bit BCD adder using IC 7483

The 8-bit BCD adder using the 4-bit BCD adder using 7483 is shown in the figure below.

We have to use two 4-bit adders. the carry-out of the lower 4-bit adder is applied to carry input of the next 4-bit adder.

The concept of adding 6 (0110) for correction purposes is used in this circuit as well.

You can learn the IC 7483 datasheet from the below link:

Also Read: 4 Bit Binary To BCD Converter

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BCD Adder Circuit | BCD Adder Truth Table | BCD Adder Block Diagram:

The digital systems handles the decimal number in the form of binary coded decimal numbers (BCD). A BCD Adder Circuit that adds two BCD digits and produces a sum digit also in BCD. BCD numbers use 10 digits, 0 to 9 which are represented in the binary form 0 0 0 0 to 1 0 0 1, i.e. each BCD digit is represented as a 4-bit binary number. When we write BCD number say 526, it can be represented as

Here, we should note that BCD cannot be greater than 9.

The addition of two BCD numbers can be best understood by considering the three cases that occur when two BCD digits are added.

Sum Equals 9 or less with carry 0

Let us consider additions of 3 and 6 in BCD.

The addition is carried out as in normal binary addition and the sum is 1 0 0 1, which is BCD code for 9.

Sum greater than 9 with carry 0

Let us consider addition of 6 and 8 in BCD

The sum 1 1 1 0 is an invalid BCD number. This has occurred because the sum of the two digits exceeds 9. Whenever this occurs the sum has to be corrected by the addition of six (0110) in the invalid BCD number, as shown below

After addition of 6 carry is produced into the second decimal position.

Sum equals 9 or less with carry 1

Let us consider addition of 8 and 9 in BCD

In this, case, result (0001 0001) is valid BCD number, but it is incorrect. To get the correct BCD result correction factor of 6 has to be added to the least significant digit sum, as shown below

Going through these three cases of BCD addition we can summarise the BCD addition procedure as follows :

• Add two BCD numbers using ordinay binary addition.
• If four-bit sum is equal to or less than 9, no correction is needed. The sum is in proper BCD form.
• If the four-bit sum is greater than 9 or if a carry is generated from the four-bit sum, the sum is invalid.
• To correct the invalid sum, add 0110 2 to the four-bit sum. If a carry results from this addition, add it to the next higher-order BCD digit.

Thus to implement BCD Adder Circuit we require :

• 4-bit binary adder for initial addition
• Logic circuit to detect sum greater than 9 and
• One more 4-bit adder to add 0110 2 in the sum if sum is greater than 9 or carry is 1.

The logic circuit to detect sum greater than 9 can be determined by simplifying the boolean expression of given BCD Adder Truth Table.

With this design information we can draw the BCD Adder Block Diagram, as shown in the Fig. 3.32.

As shown in the Fig. 3.32 , the two BCD numbers, together with input carry, are first added in the top 4-bit binary adder to produce a binary sum. When the output carry is equal to zero (i.e. when sum ≤ 9 and C out = 0) nothing (zero) is added to the binary sum. When it is equal to one (i.e. when sum > 9 or C out = 1), binary 0110 is added to the binary sum through the bottom 4-bit binary adder. The output carry generated from the bottom binary adder can be ignored, since it supplies information already available at the output-carry terminal.

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Design And Implementation of a BCD Adder Circuit Using IC-7483

In this project, we are implementing and designing a BCD Adder circuit using IC-7483. The objective of this experiment is to fully understand and implement of addition of two BCD numbers and get the result in BCD form.

Must Read Tutorial Projects

This arithmetic circuit accepts two BCD numbers as the augend and addend at its two 4-bit inputs and produces their sum in the same code (BCD code). The BCD adder is usually complicated compared to the binary adder. Because of the fact that some of the sum outputs don’t belong to the group of BCD codes. If the sum of the two BCD inputs along with a carry-in bit gives the decimal 9 (1001) or less, then the sum represents the valid BCD sum. But the problem arises if the sum exceeds BCD codes of decimal 9.

Since each input BCD digit may be a maximum of 9, then considering an input carry of 1, the sum of the two BCD digits may be a maximum of 19 = (9+9+1). But the sum which is greater or equal to decimal 10 but less than or equal to decimal 19 can’t be represented by a 4-Bit valid BCD code. It requires two 4-Bit groups of valid BCD code. For example, consider the sum of 3+9.

3 {0011} + 9 {1001} = 12 {1100}

The resulting sum of 1100 is not a valid BCD code of decimal 12. The correct answer should be 0001 0010. The below table shows the corrected BCD for all possible sum outputs from a 4-bit binary adder, adding BCD augend and addend. It may be noted from the table that the corrected BCD form can be obtained from the sum output simply by adding 6 (0110) to it when the sum is greater than 9 but less or equal to 19.

Table of Contents

Circuit Diagram

Components Required

• 7483 Adder IC (x2)
• 7485 Comparator IC
• 7404 NOT Gate IC
• 3 Terminal Switch (x8)
• 4 LED (S3-S0)
• +5V Power Supply

Circuit Connection of BCD Adder Circuit

Now we can use IC-7485, the 4-bit magnitude comparator and an OR gate shown in Fig 1 to make the correction circuit. One 4-bit input (B 3 , B 2 , B 1 , B 0 ) of the comparator is connected to 1001 (9 10 ), and the other 4-bit input (A 3 , A 2 , A 1 , A 0 ) of the comparator is connected to the outputs (S 3 , S 2 , S 1 , S 0 ) of the full adder, FA 1 . The (A>B) output of the comparator and the C out of the FA 1 adder is connected with the OR gate inputs. The output of the OR gate is connected to the B 1 and B 2 input of the FA 2 full adder. Finally, connect B 3 and B 0 with the ground.

When the sum output S 3 ‘, S 2 ‘, S 1 ‘, S 0 ‘ is greater than 9 10 or C out of FA 1 is 1, the OR gate output becomes 1 for which 0110 is added with S 3 ‘, S 2 ‘, S 1 ‘, S 0 ‘ by the FA 2 because B2 and B1 both become 1 under this situation. But the comparator output (A>B) = 0 and C out = 0 (the carry-out of FA 1 ) when the sum output from (full adder) 1 is less than 9 or maximum equal to 9. Therefore the B1 and B2 inputs of (full adder) 2 are 0 and no correction is done because 0000 is added to (S 3 ‘, S 2 ‘, S 1 ‘, S 0 ‘) by (full adder) 2 .

ICs Used for Making The BCD Adder Circuit

Ic-7483 (4-bit binary adder ).

The IC-7483 is a commonly available TTL 4-bit parallel adder chip. It contains four interconnected full adders; a look-ahead carry circuitry for its operation (CLA = Carry Look-Ahead Adder). The logic symbol of IC7483 is shown in fig 2 and the pin configuration in table 1. It has two 4-bit A 3 , A 2 , A 1 , A 0 and B 3 , B 2 , B 1 , B 0 and a carry input C in in the LSB stage. The outputs are a 4-bit sum S 3 , S 2 , S 1 , S 0 and a carry output (C out ) from the MSB stage.

Two or more parallel adder blocks can be connected in a cascade to perform the addition operation on a larger binary number. The four LSB of the number is added in the first adder. The carry output of this adder is given as carrying input to the second adder, which adds the four MSB of the number. the output carry of the second adder is the final carry output.

IC-7485 (4-Bit Magnitude Comparator)

The IC-7485 is a 4-bit magnitude comparator of the TTL family. The circuit diagram is shown in fig 3. This IC compares the magnitudes of two 4-bit numbers; A 3 , A 2 , A 1 , A 0 . and B 3 , B 2 , B 1 , B 0 . This IC has three outputs (A>B) out ; (A=B) out and (A<B) out . Besides those pins, this IC has cascading facilities. These cascading inputs are (A>B) in ; (A=B) in and (A<B)in. When the two inputs are equal then the outputs of the chip become a function of cascading inputs.

IC-7432 (OR Gate)

The IC-7432 is a member of gate ICs and has the functionality of an OR gate or function. It will give high if either all or any one of the two inputs is high. IC-7432 has 4 OR gates of 2 inputs in 1 package. The internal gates are made of from Schottky Transistor of low power.

Truth Tables for BCD Adder Circuit

Table 1: Truth table for comparator IC-7485

Where A and B are inputs and all three Y’s values are outputs.

Table 2: Theoretical truth table for binary and corrected BCD numbers

Table 3: Theoretical truth table for the addition of two BCD numbers and getting the result in BCD [C in =0 and C in =1 in both cases]

Table 2 shows the correction is needed under the following condition:-

• If the carry out of the 4-bit binary full adder is 1 after the addition of two BCD digits.
• If the sum bits S 2 ‘ and S 3 ‘ of the binary full adder are such that S 2 ‘S 3 ‘=1.
• If the sum bits S 1 ‘ and S 3 ‘ of the binary full adder are such that S 1 ‘S 3 ‘=1.

These three conditions can be combined to form an expression as

X = C 3 ‘+S 2 ‘S 3 ‘+S 1 ‘S 3 ‘

This expression for X shows that if X=1 then we used to take the help of BCD correction (by adding 6 to the valid BCD). Based on this expression we may design a correction circuit that will produce (x=1) when the sum output is not a valid BCD and adds 6 (0110) to the invalid BCD output from the binary adder. When this correction circuit produces X=0, then the sum output from the adder is less than or equal to 9 and no correction is required.

Table 4 for OR Gate used within the circuit configuration (IC-7432)

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PhysicsTeacher.in

High School Physics

BCD Adder Design

In this post, we are going to discuss BCD Adder Design steps.

A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit which is also in BCD. A BCD adder must include the correction logic (i.e. add 6 command) in its internal construction. A block diagram for the BCD adder is shown in figure1. The block diagram shows that the BCD adder contains two 4-bit binary adders and one combinational logic circuit. This combinational circuit is used to generate the add 6 command.

Characteristics of a BCD Adder

A BCD adder circuit must be able to do the following:

•  Add two BCD numbers using straight binary addition.
• If the Sum<=9 and carry=0, the sum is in proper BCD form and no correction is needed.
• If the Sum > 9 or if a carry=1, the sum is not in proper BCD form. Then, correction is required and the digit 6(0110) should be added to the sum to produce the BCD results. The carry may be produced due to this addition and it is added to the next decimal position.

Design of combinational circuit to generate add 6 command

To design a combinational circuit first draw the truth table for it. Figure 2 shows the truth table. The inputs for the circuit are S 3 S 2 S 1 S 0 of adder-1 and Y is the output. Output remains 0 till the Sum<=9 and carry=0 and Y=1 for Sum > 9 or if a carry=1.

Now solve the K-map for output Y which is shown in figure 3.

Now from the K-map, it is clear that the output (Y) of the combinational circuit is Y= S3S2 + S3S1, and carry of adder-1 (C out ) is again OR-ed with the output Y to generate the final output Y’.

Therefore, the condition for correction can be written as an expression as follows: Y’ = S 3 S 2 + S 3 S 1 + C out So the corrected BCD adder circuit is shown in Figure 4.

Working operation of BCD adder

The circuit diagram of a BCD adder shows that the output of the combinational circuit must be 1 if C out of adder-1 is high. Therefore, Y is OR-ed with C out of adder 1 as shown in figure 4.

The output of combinational circuit Y’ is then connected to B2B1 inputs of adder-2 and B3=B1=0 as they are connected to the ground permanently. This makes B3B2B1B0=0110 if Y’=1.The sum outputs of adder-1 are applied to A3 A2 A1 A0 of adder-2.

The output of the combinational circuit is to be used as the final carry output and the carry output of adder-2 is to be ignored.

Then the operation of a BCD adder shown in Figure 4 is explained as follows: the first stage of the adder adds two 4-bit BCD numbers, and its sum (S 3 S 2 S 1 S 0 ) and carry (C out ) are checked for the following cases.

CASE-I:  Sum<=9 and carry=0

The output of combinational circuit Y’=0. Hence, B 3 B 2 B 1 B 0 =0000 for adder-2. Therefore, the output of adder-2 is the same as that of adder-1.

CASE-II:  Sum > 9 and carry=0

S 3 S 2 S 1 S 0 of adder-1 is greater than 9, and then the output Y of the combinational circuit becomes 1. Therefore, B3B2B1B0=0110 (of adder-2). Hence, six (0110) will be added to the sum output of adder-1. We get the corrected BCD result at the output of adder-2.

CASE-III:  Sum <=9 but carry=1

As the carry output of adder-1 is high, we have, Y’=1. Therefore, B 3 B 2 B 1 B 0 =0110(of adder-2)

Hence, 0110 will be added to the sum output of adder-1. We get the corrected BCD result at the output of adder-2. Thus, the four bit BCD addition can be carried out using the binary adder.

Author of this post

This post is co-authored by Professor Saraswati Saha , who is an assistant professor at RCCIIT, a renowned degree engineering college in India. Professor Saha teaches subjects related to digital electronics & microprocessors.

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Rugved Mhatre

MS. Computer Engineering @NYU Ex-Oracle

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Single Digit BCD Adder

1 minute read

I assisted my college professor in recording a video demonstration of the experiment, which aimed to showcase the working of a single digit BCD adder.

A single digit Binary Coded Decimal (BCD) adder is a digital circuit that performs the addition of two BCD numbers, each represented by a 4-bit binary code. BCD is a way of representing decimal numbers using binary code, where each digit of the decimal number is represented by 4 bits. A single digit BCD adder performs the addition of two BCD numbers, one bit at a time, and outputs the sum as a 4-bit BCD code.

In a single digit BCD adder, the two input BCD numbers are first converted to binary, and then the binary addition is performed. The result of the binary addition is a 4-bit BCD code representing the sum of the two input BCD numbers, which is converted back to decimal to get the result.

The experiment involved using an integrated circuit (IC) to implement the BCD adder, and the video demonstrated the various steps involved in the process, including the circuit setup, input and output signals, and the final result.

My role was to ensure that the experiment was recorded in high quality and with clear audio, so that the viewers could easily understand the details of the experiment. The video was edited to highlight the key aspects of the experiment and to provide a clear and concise explanation of the working of a single digit BCD adder.

Overall, it was a great experience working on this project and contributing to the advancement of knowledge in the field of digital electronics. We are proud to have played a small part in this experiment and hope that the video will be a valuable resource for students and professionals alike.

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Design of QCA-Based BCD Adder

• Conference paper
• First Online: 07 February 2023
• Cite this conference paper

• S. Javeed Basha 40 ,
• B. Shilpa 40 ,
• A. Vyshnavi 40 ,
• Y. Soma Sundar Reddy 40 &
• C. Sudharshan 40  

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 947))

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IC technology advances daily in order to improve device efficiency and density of small devices. For the last 4 decades, standard CMOS technology has been a critical component of digital computing. However, scaling CMOS systems has been a struggle over the previous several years. QCA has indeed been recognized as a unique nanoelectronic technology. To provide a novel idea of integrated circuit design in an effective and optimal way, an effective design for BCD adders in QCA technology has been given here, utilizing an area optimized QCA complete adder. In compared to previous BCD adder design, the suggested BCD adder circuit optimizes QCA design parameters including such layout area, as well as number of QCA cells.

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Javeed Basha, S., Shilpa, B., Vyshnavi, A., Soma Sundar Reddy, Y., Sudharshan, C. (2023). Design of QCA-Based BCD Adder. In: Kumar, A., Senatore, S., Gunjan, V.K. (eds) ICDSMLA 2021. Lecture Notes in Electrical Engineering, vol 947. Springer, Singapore. https://doi.org/10.1007/978-981-19-5936-3_85

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For Lab: OBJECTIVE: DESIGN AND SIMULATE A 4-BIT BCD ADDER

Created: Dec 29, 2021

Updated: Aug 27, 2023

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• Engineering Mathematics
• Discrete Mathematics
• Operating System
• Computer Networks
• Digital Logic and Design
• C Programming
• Data Structures
• Theory of Computation
• Compiler Design
• Computer Org and Architecture

Adders and Subtractors in Digital Logic

• Full Subtractor in Digital Logic
• Half Subtractor in Digital Logic
• Serial Binary Adder in Digital Logic
• BCD Adder in Digital Logic
• Full Adder in Digital Logic
• Half Adder in Digital Logic
• Array Multiplier in Digital Logic
• Half Adder and Half Subtractor using NAND NOR gates
• Binary Representations in Digital Logic
• Digital Electronics and Logic Design Tutorials
• Parallel Adder and Parallel Subtractor
• Consensus Theorem in Digital Logic
• 4-bit binary Adder-Subtractor
• Digital Logic Design - Quiz Questions
• Multiplexers in Digital Logic
• Non-binary Counter in Digital Logic
• Encoders and Decoders in Digital Logic
• What is Digital Logic ?
• Addition and Subtraction of Decimals

Subtraction of two binary numbers can be accomplished by adding 2’s complement of the subtrahend to the minuend and disregarding the final carry if any. If the MSB bit in the result of addition is a ‘0’. then the result of addition is the correct answer. If the MSB bit is a ‘1’. , this implies that the answer has a negative sign. The true magnitude, in this case, is given by 2’s complement of the result of the addition.

Points to Remember on Combinational Logic Circuit:

• Output depends upon the combination of inputs.
• Output is a pure function of present inputs only i.e., Previous State inputs won’t have any effect on the output. Also, It doesn’t use memory.
• In other words,
• Inputs are called Excitation from circuits and outputs are called Responses of combinational logic circuits.

Classification of Combinational Logic Circuits:  

1. Arithmetic:

• Subtractors
• Multipliers
• Comparators

2. Data Handling:

• Multiplexers
• DeMultiplexers
• Encoders and Decoders

3. Code Converters:

• BCD to Excess-3 code and vice versa
• BCD to Gray code and vice versa
• Seven Segment

Design of Half Adders and Full Adders:

• A combinational logic circuit that performs the addition of two single bits is called Half Adder.
• A combinational logic circuit that performs the addition of three single bits is called Full Adder.

1. Half Adder :

• It is a arithmetic combinational logic circuit designed to perform addition of two single bits.
• It contain two inputs and produces two outputs.
• Inputs are called Augend and Added bits and Outputs are called Sum and Carry.

Let us observe the addition of single bits ,

Since 1+1=10, the result must be two bit output. So, Above can be rewritten as,

The result of 1+1 is 10, where ‘1’ is carry-output (C out ) and ‘0’ is Sum-output (Normal Output). 

Truth Table of Half Adder:

Next Step is to draw the Logic Diagram. To draw Logic Diagram, We need Boolean Expression, which can be obtained using K-map (karnaugh map) . Since there are two output variables ‘S’ and ‘C’, we need to define K-map for each output variable. 

K-map for output variable Sum ‘S’:

 K-map is of Sum of products form. The equation obtained is

which can be logically written as,

K-map for output variable Carry ‘C’:

The equation obtained from K-map is,

Using the Boolean Expression, we can draw logic diagram as follows..

Limitations: Adding of Carry is not possible in Half adder. 

2. Full Adder :  

• To overcome the above limitation faced with Half adders, Full Adders are implemented.
• It is a arithmetic combinational logic circuit that performs addition of three single bits.
• It contains three inputs (A, B, C in ) and produces two outputs (Sum and C out ).
• Where, C in -> Carry In and C out -> Carry Out

Truth table of Full Adder:

The equation obtained is,

The equation can be simplified as,

K-map Simplification for output variable ‘C out ‘

3. Half Subtractor :

• It is a combinational logic circuit designed to perform the subtraction of two single bits.
• It contains two inputs (A and B) and produces two outputs (Difference and Borrow-output).

Truth Table of Half Subtractor:

  K-map Simplification for output variable ‘D’:

K-map Simplification for output variable ‘B out ‘ :

The equation obtained from above K-map is,

Logic Diagram of Half Subtractor:

4. Full Subtractor :

• It is a Combinational logic circuit designed to perform subtraction of three single bits.
• It contains three inputs(A, B, B in ) and produces two outputs (D, B out ).
• Where, A and B are called Minuend and Subtrahend bits.
• And, B in -> Borrow-In and B out -> Borrow-Out

Truth Table of Full Subtractor:

which can be simplified as,

• For performing arithmetic calculations in electronic calculators and other digital devices.
• In Timers and Program Counters.
• Useful in Digital Signal Processing.

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BCD full adder subtraction and addition

I want to design a circuit that takes as input two decimal digits binary coded as A1…4 and subtractionB1…4 and displays their , sum or (fulldifference using a two place BCD-to-7-segment display as selected by a signal C : A BCD adder)/subtractor.

I use full adder(s), (and), (xor) and (or) gates, Also I used input C carry in for subtraction, but the BCD circuit doesn't work like the way I want. When I use the A1 and B1 inputs, the result at the outputs will be incorrect . The other inputs work well. When I use carry, the subtraction of inputs, gives me an incorrect output value

The outputs can't be bigger than 15 in the process of additio,and cannot be negative in the subtraction process.

For example when I put 4+6 in inputs, the result of output will be 10. When I put 8+8, the result, the output will be 15. For some reasons the output cannot give me numbers bigger than 15.

In the process of subtractor, can't gives me negative numbers. For example, when I put 1-2 in inputs, the output will gives me 6.

• digital-logic
• circuit-design

• \$\begingroup\$ Does this answer your question? BCD adder and subtractor \$\endgroup\$ –  toolic Commented Feb 8, 2023 at 13:57
• \$\begingroup\$ Yes, I modified the circuit a little, but another problem appeared \$\endgroup\$ –  Mohammed Al-Elaiwi Commented Feb 8, 2023 at 13:59
• \$\begingroup\$ If i put 4+5 in inputs, the outputs will be 9. But when i put 8+8 in inputs, than outputs will be 15. the outputs cannot gives me number bigger than 15 for some reasons. \$\endgroup\$ –  Mohammed Al-Elaiwi Commented Feb 8, 2023 at 14:23
• 1 \$\begingroup\$ the schematic is incorrect. why did you choose this schematic? can you post a link to any reference material you used in choosing this schematic? \$\endgroup\$ –  toolic Commented Feb 8, 2023 at 15:32
• 1 \$\begingroup\$ @PeterJennings: That's because the OP deleted that question and you do not have privileges to see deleted questions. \$\endgroup\$ –  toolic Commented Feb 8, 2023 at 17:50

Your initial addition portion:

... is just fine. You've got that right. And it's standard practice. You should be able to see that the 5 bits exiting the output will obey the usual rules.

For example, in the case you mentioned, of 8 + 8, you should see that the carry out will be 1 while the remaining four bits are all 0 . And in the other case you mentioned, 1 - 2, you should see the carry out is 0 and the other four bits are all 1 .

That's what should happen in 4-bit binary.

• A problem comes in when displaying a result. For example, if the carry out is 0 and you are subtracting, then the result is a negative value and you need to display a - , somehow. You need a way to show that the result is negative. I gather from your comments (not stated in the question) that you are thinking of just using an LED to indicate this.
• Another problem is that for subtraction where negative results occur, you need to convert that back to an absolute value -- which means complementing it back and adding 1 again -- in order to generate the lower digit needed to be displayed (with a minus sign, somehow.)
• A final problem comes during addition and when anything over the value of the value of 2*4+1=9 is generated. In this case, 2*3=6 must be added. (Since the lower bit is 0 , this really means adding 3 to the middle 3 bits.) Suppose you have the output of 10 (01010.) Then to generate a BCD output you add 00110 to that: 01010 + 00110 = 10000. This gives the BCD result of 1 and 0 that you need to show 10 on the display. (Note that this operation has to occur whether the result is positive or negative, but that it must occur after step 2 has been dealt with and not beforehand.)

What's the plan to achieve the above?

Here's my thought. (Which also includes greybeard 's note that I already know to expect a 1 in the tens display when I'm adding 3 in the 2nd 7483. So one less gate needed, now. Thanks!)

• \$\begingroup\$ You already generate a signal decimal carry in addition : this is the LSB of the more significant digit, you don't need to recompute it from S1…4, saving at least the uppermost AND with one inverted input . \$\endgroup\$ –  greybeard Commented Feb 9, 2023 at 13:42
• \$\begingroup\$ @greybeard Okay. Thanks. I think I see my folly. Yeah. If I'm adding 3 (6), then it must be because I expect to see a 1 in the tens digit. (I'm an idiot!) I'll make the adjustment. And thanks! \$\endgroup\$ –  periblepsis Commented Feb 9, 2023 at 22:38
• \$\begingroup\$ @greybeard I think the questioner is stuck with 7483s, whether mentally or by outside requirements. I've not used the 4000 series devices. (Too expensive, too few in variety, too difficult to find, and I never did lay hands on an RCA databook back when I was in my multi-board wire-wrapping days.) And thanks again for the kick in the head! \$\endgroup\$ –  periblepsis Commented Feb 10, 2023 at 18:26
• \$\begingroup\$ I tried your design, it can give me output 9 + 9 = 18, but for some reasons the output can't give me 17 and 1, and another problem if i put 0-8 it gave me -7, also it give me hexadecimal number in subtractor \$\endgroup\$ –  Mohammed Al-Elaiwi Commented Feb 11, 2023 at 23:25
• \$\begingroup\$ @Mohammed Then you didn't get the right schematic. Here's the 0 - 8 = -8 example . You can see it works fine. And here's the 9+8 = 17 example . It also works fine. I've thoroughly checked it out. It works in every single case. I also automated the testing, as well. It's possible you may need to learn a little more about your simulator. \$\endgroup\$ –  periblepsis Commented Feb 12, 2023 at 0:23

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