signal assignment in vhdl example

• Product Manual
• Knowledge Base
• Release Notes
• Tech Articles
• Screencasts

Signal Assignments in VHDL: with/select, when/else and case

Sometimes, there is more than one way to do something in VHDL. OK, most of the time , you can do things in many ways in VHDL. Let’s look at the situation where you want to assign different values to a signal, based on the value of another signal.

With / Select

The most specific way to do this is with as selected signal assignment. Based on several possible values of a , you assign a value to b . No redundancy in the code here. The official name for this VHDL with/select assignment is the selected signal assignment .

When / Else Assignment

The construct of a conditional signal assignment is a little more general. For each option, you have to give a condition. This means that you could write any boolean expression as a condition, which give you more freedom than equality checking. While this construct would give you more freedom, there is a bit more redundancy too. We had to write the equality check ( a = ) on every line. If you use a signal with a long name, this will make your code bulkier. Also, the separator that’s used in the selected signal assignment was a comma. In the conditional signal assignment, you need the else keyword. More code for the same functionality. Official name for this VHDL when/else assignment is the conditional signal assignment

Combinational Process with Case Statement

The most generally usable construct is a process. Inside this process, you can write a case statement, or a cascade of if statements. There is even more redundancy here. You the skeleton code for a process (begin, end) and the sensitivity list. That’s not a big effort, but while I was drafting this, I had put b in the sensitivity list instead of a . Easy to make a small misstake. You also need to specify what happens in the other cases. Of course, you could do the same thing with a bunch of IF-statements, either consecutive or nested, but a case statement looks so much nicer.

While this last code snippet is the largest and perhaps most error-prone, it is probably also the most common. It uses two familiar and often-used constructs: the process and the case statements.

Hard to remember

The problem with the selected and conditional signal assignments is that there is no logic in their syntax. The meaning is almost identical, but the syntax is just different enough to throw you off. I know many engineers who permanenty have a copy of the Doulos Golden Reference Guide to VHDL lying on their desks. Which is good for Doulos, because their name gets mentioned all the time. But most people just memorize one way of getting the job done and stick with it.

• VHDL Pragmas (blog post)
• Records in VHDL: Initialization and Constraining unconstrained fields (blog post)
• Finite State Machine (FSM) encoding in VHDL: binary, one-hot, and others (blog post)
• "Use" and "Library" in VHDL (blog post)
• The scope of VHDL use clauses and VHDL library clauses (blog post)

• Network Sites:
• Technical Articles
• Market Insights

• Or sign in with
• iHeartRadio

Concurrent Conditional and Selected Signal Assignment in VHDL

Join our engineering community sign-in with:.

This article will review the concurrent signal assignment statements in VHDL.

This article will first review the concept of concurrency in hardware description languages. Then, it will discuss two concurrent signal assignment statements in VHDL: the selected signal assignment and the conditional signal assignment. After giving some examples, we will briefly compare these two types of signal assignment statements.

Please see my article introducing the concept of VHDL if you're not familiar with it.

Concurrent vs. Sequential Statements

To understand the difference between the concurrent statements and the sequential ones, let’s consider a simple combinational circuit as shown in Figure 1.

Figure 1. A combinational circuit.

If we consider the operation of the three logic gates of this figure, we observe that each gate processes its current input(s) in an independent manner from other gates. These physical components are operating simultaneously. The moment they are powered, they will “concurrently” fulfill their functionality. Note that while, in practice, the AND gate has a delay to produce a valid output, this does not mean that the OR gate will stop its functionality and wait until the output of the AND gate is produced. The OR gate will function all the time; however, its output will not be valid until its inputs have settled.

Now, let’s examine the VHDL description of Figure 1. This is shown below:

The main part that we are here interested in is the definition of the three gates:

Each of these lines describes a physical component in Figure 1. For example, the second line, which describes the OR gate, takes sig1 and c as inputs and produces the OR of these two values. We saw that the physical components of Figure 1 operate concurrently. Hence, it is reasonable to expect that the VHDL description of these gates should be evaluated in a concurrent manner. In other words, the above three lines of the code are executed at the same time and there is no significance to the order of these statements. As a result, we can rewrite the architecture section of the above code as below:

Since these statements are evaluated at the same time, we call them concurrent statements. This type of code is quite different from what we have learned in basic computer programming where the lines of code are executed one after the other. For example, consider the following MATLAB code:

This code produces out1=1 and out2=1 . However, if we change the order of the statements to the following, the program will stop working because we are trying to use sig1 before it is generated.

While the VHDL code describing Figure 1 was executed concurrently, the above MATLAB code is evaluated sequentially (i.e., one line after the other). VHDL supports both the concurrent statements and the sequential ones. It's clear that the concurrent VHDL statements will allow us to easily describe a circuit such as the one in Figure 1 above. In a future article, we'll see that the sequential VHDL statements allow us to have a safer description of sequential circuits. Furthermore, using the sequential VHDL, we can easily describe a digital circuit in a behavioral manner. This capability can significantly facilitate digital hardware design.

The following figure illustrates the difference between concurrent and sequential statements.

Figure 2. The difference between concurrent and sequential statements. Image courtesy of VHDL Made Easy .

Now let's take a look at two concurrent signal assignment statements in VHDL: “the selected signal assignment statement” and “the conditional signal assignment statement”.

Selected Signal Assignment or the “With/Select” Statement

Consider an n -to-one multiplexer as shown in Figure 3. This block should choose one out of its n inputs and transfer the value of this input to the output terminal, i.e., output_signal .

Figure 3. A multiplexer selects one of its n inputs based on the value of the control_expression.

The selected signal assignment allows us to implement the functionality of a multiplexer. For example, the VHDL code describing the multiplexer of Figure 3 will be

Here, the value of the control_expression will be compared with the n possible options, i.e., option_1 , option_2 , …, option_n . When a match is found, the value corresponding to that particular option will be assigned to the output signal, i.e., output_signal . For example, if control_expression is the same as option_2 , then value_2 will be assigned to the output_signal .

Note that the options of a “with/select” assignment must be mutually exclusive, i.e., one option cannot be used more than once. Moreover, all the possible values of the control_expression must be included in the set of the options. The following example clarifies these points.

Example 1 : Use the "with/select" statement to describe a one-bit 4-to-1 multiplexer. Assume that the inputs to be selected are a , b , c , and d . And, a two-bit signal, sel , is used to choose the desired input and assign it to out1 .

The code for this multiplexer is given below:

Note that since the std_logic data type can take values other than “0” and “1” , the last line of the “with/select” statement needs to use the keyword “ others ” to take all the possible values of sel into account.

The following figure shows the simulation of this code using the Xilinx ISE simulator. (In case you’re not familiar with ISE, see this tutorial .) As shown in this figure, from 0 nanosecond (ns) until 300 ns the select input, sel , is 00, and, hence, out1 follows the input a . Similarly, you can verify the intended operation for the rest of the simulation interval.

Figure 4. The ISE simulation for the multiplexer of Example 1.

Example 2 : Use the “with/select” statement to describe a 4-to-2 priority encoder with the truth table shown below.

The following VHDL code can be used to describe the above truth table:

The ISE simulation is shown in Figure 5.

Figure 5. The ISE simulation for the priority encoder of Example 2.

Conditional signal assignment or the “when/else” statement.

The “when/else” statement is another way to describe the concurrent signal assignments similar to those in Examples 1 and 2. Since the syntax of this type of signal assignment is quite descriptive, let’s first see the VHDL code of a one-bit 4-to-1 multiplexer using the “when/else” statement and then discuss some details.

Example 3 : Use the when/else statement to describe a one-bit 4-to-1 multiplexer. Assume that the inputs to be selected are a , b , c , and d . And, a two-bit signal, sel , is used to choose the desired input and assign it to out1 .

The code will be

In this case, the expressions after “when” are evaluated successively until a true expression is found. The assignment corresponding to this true expression will be performed. If none of these expressions are true, the last assignment will be executed. In general, the syntax of the “when/else” statement will be:

We should emphasize that the expressions after the “when” clauses are evaluated successively. As a result, the expressions evaluated earlier has a higher priority compared to the next ones. Considering this, we can obtain the conceptual diagram of this assignment as shown in Figure 6. This figure illustrates a conditional signal assignment with three “when” clauses.

Figure 6. The conceptual implementation of a “when/else” statement with three “when” clauses.

Let’s review the main features of the selected signal assignment and the conditional signal assignment.

“With/Select” vs. “When/Else” Assignment

As mentioned above, the options of a “with/select” assignment must be mutually exclusive, i.e., one option cannot be used more than once. Moreover, all the possible values of the control_expression must be included in the set of options. While the “with/select” assignment has a common controlling expression, a “when/else” assignment can operate on expressions with different arguments. For example, consider the following lines of code:

In this case, the expressions are evaluating two different signals, i.e., reset1 and clk .

For the “when/else” assignment, we may or may not include all the possible values of the expressions to be evaluated. For example, the multiplexer of Example 3 covers all the possible values of sel ; however, the above code does not. The above code implies that out1 should retain its previous value when none of the expressions are true. This causes the inference of a latch in the synthesized circuit.

Another important difference between the “with/select” and “when/else” assignment can be seen by comparing the conceptual implementation of these two statements. The priority network of Figure 6 involves a cascade of several logic gates. However, the “with/select” assignment avoids this chain structure and has a balanced structure. As a result, in theory, the “with/select” statement may have better performance in terms of the delay and area (see RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability , Xilinx HDL Coding Hints , and Guide to HDL Coding Styles for Synthesis ).

In practice, we generally don’t see this difference because many synthesis software packages, such as the Xilinx XST, try not to infer a priority encoded logic. Though we can use the PRIORITY_EXTRACT constraint of XST to force priority encoder inference, Xilinx strongly suggests that we use this constraint on a signal-by-signal basis; otherwise, the constraint may guide us towards sub-optimal results. For more details see page 79 of the XST user guide .

• Concurrent statements are executed at the same time and there is no significance to the order of these statements. This type of code is quite different from what we have learned in basic computer programming where the lines of code are executed one after the other.
• The selected signal assignment or the "with/select" assignment allows us to implement the functionality of a multiplexer.
• The options of a “with/select” assignment must be mutually exclusive, i.e., one option cannot be used more than once. Moreover, all the possible values of the control_expression must be included in the set of the options.
• For the "when/else" statement, the expressions after the “when” clauses are evaluated successively. As a result, the expressions evaluated earlier has a higher priority compared to the next ones.
• One important difference between the “with/select” and “when/else” assignment can be seen by comparing the conceptual implementation of these two statements. The "when/else" statement has a priority network; however, the “with/select” assignment avoids this chain structure and has a balanced structure.

To see a complete list of my articles, please visit  this page .

  Featured image used courtesy of Parallella .

Related Content

• Safety in Sensing: Sensor Technology in Smart Cities
• Thermocouple Signal Conditioners and Signal Conditioning Near the Cold Junction
• Test & Measurement in Quantum Computing
• Reducing Distortion in Tape Recordings with Hysteresis in SPICE
• Open RAN – Network Performance in the Lab and in the Field
• Looking for Good Waves: The Importance of Signal Integrity in High-Speed PCB Design

Learn More About:

• programmable logic

Great content. The link to the ISE guide requires password. Can we get that posted again? Thanks!

You May Also Like

Infineon’s Commitment Towards Decarbonization and Digitalization

In Partnership with Future Electronics

Oscilloscope Measurements to Satisfy Full-Bridge Converter Verification Requirements

by Rohde & Schwarz

Nuvoton’s New MCU Balances Low Power Consumption and Speed

by Jake Hertz

Innovation Shined at Embedded World 2024

by Jeff Child

Key Concepts of Magnetic Materials

by Dr. Steve Arar

Welcome Back

Don't have an AAC account? Create one now .

Forgot your password? Click here .

Chapter 3 - Data Flow Descriptions

Section 6 - signal assignments.

A signal assignment statement modifies the target signal

Description:

A Signal assignment statement can appear inside a process (sequential statement) or directly in an architecture (concurrent statement). The target signal can be either a name (simple, selected, indexed, or slice) or an aggregate .

A signal assignment with no delay (or zero delay) will cause an event after delta delay, which means that the event happens only when all of the currently active processes have finished executing (i.e. after one simulation cycle).

The default delay mode ( inertial ) means that pulses shorter than the delay (or the reject period if specified) are ignored. Transport means that the assignment acts as a pure delay line.

VHDL'93 defines the keyword unaffected which indicates a choice where the signal is not given a new assignment. This is roughly equivalent to the use of the null statement within case (see Examples).

• Delays are usually ignored by synthesis tool.

Aggregate , Concurrent statement , Sequential statement , Signal , Variable assignment

Chapter 3 - Data Flow Descriptions

Section 1 - a first example.

In VHDL -93, any signal assignment statement may have an optional label:

Designing Circuits with VHDL

1. introduction, 2. combinational circuits, signal assignments in vhdl.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fullAdder is     port(  A,B: in  std_logic;  -- input bits for this stage            Ci:   in  std_logic; -- carry into this stage            S:    out std_logic; -- sum bit            Co:   out std_logic  -- carry out of this stage     ); end fullAdder; architecture a1 of fullAdder is begin     S <= A xor B xor Ci;     Co <= (A and B) or ((A xor B) and Ci); end a1;

Processes and Conditional Statements

if a = '0' then     x <= a;     y <= b; elsif a = b then     x <= '0';   y <= '1'; else     x <= not b; y <= not b; end if;

Every signal that is assigned a value inside a process must be defined for all possible conditions.

Case Statements

Structural vhdl, 3. sequential circuits.

busy   is high when the circuit is in the middle of performing an operation;             while busy is high, the insert and delete inputs are ignored; the             outputs are not required to have the correct values when busy is high empty     is high when there are no pairs stored in the priority queue; delete             operations are ignored in this case full      is high when there is no room for any additional pairs to be stored;             insert operations are ignored in this case

• For adjacent pairs in the bottom row, the pair to the left has a key that is less than or equal to that of the pair on the right.
• For pairs that are in the same column, the key of the pair in the bottom row is less than or equal to that of the pair in the top row.
• In both rows, the empty blocks (those with dp =0) are to the right and either both rows have the same number of empty blocks or the top row has one more than the bottom row.

entity priQueue is     Port (clk, reset : in std_logic;           insert, delete : in std_logic;           key, value : in std_logic_vector(wordSize-1 downto 0);           smallValue : out std_logic_vector(wordSize-1 downto 0);           busy, empty, full : out std_logic     );    end priQueue; architecture a1 of priQueue is constant rowSize: integer := 4; -- local constant declaration type pqElement is record     dp: std_logic;     key: std_logic_vector(wordSize-1 downto 0);     value: std_logic_vector(wordSize-1 downto 0); end record pqElement; type rowTyp is array(0 to rowSize-1) of pqElement; signal top, bot: rowTyp; type state_type is (ready, inserting, deleting); signal state: state_type; begin     process(clk) begin         if rising_edge(clk) then             if reset = '1' then                 for i in 0 to rowSize-1 loop                     top(i).dp <= '0'; bot(i).dp <= '0';                 end loop;                 state <= ready;             elsif state = ready and insert = '1' then                 if top(rowSize-1).dp /= '1' then                     for i in 1 to rowSize-1 loop                         top(i) <= top(i-1);                     end loop;                     top(0) <= ('1',key,value);                     state <= inserting;                 end if;             elsif state = ready and delete = '1' then                 if bot(0).dp /= '0' then                     for i in 0 to rowSize-2 loop                         bot(i) <= bot(i+1);                     end loop;                     bot(rowSize-1).dp <= '0';                     state <= deleting;                 end if;             elsif state = inserting or state = deleting then                 for i in 0 to rowSize-1 loop                     if top(i).dp = '1' and                         (top(i).key < bot(i).key                          or bot(i).dp = '0') then                         bot(i) <= top(i); top(i) <= bot(i);                     end if;                end loop;                 state <= ready;             end if;         end if;     end process;     smallValue <= bot(0).value when bot(0).dp = '1' else                   (others => '0');     empty <= not bot(0).dp;     full <= top(rowSize-1).dp;     busy <= '1' when state /= ready else '0'; end a1;

4. Functions and Procedures

package commonConstants is     constant lgWordSize: integer := 4;        constant wordSize: integer := 2**lgWordSize; end package commonConstants; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.commonConstants.all; entity firstOne is     Port (a: in std_logic_vector(0 to wordSize-1);           x: out std_logic_vector (lgWordSize downto 0)      ); end firstOne; architecture a1 of firstOne is procedure encode(x: in std_logic_vector(0 to wordSize-1);                 indx: out std_logic_vector(lgWordSize-1 downto 0);                 errFlag: out std_logic) is -- Unary to binary encoder. -- Input x is assumed to have at most a single 1 bit. -- Indx is equal to the index of the bit that is set. -- If no bits are set, errFlag bit is made high. -- This is conceptually simple. -- --        indx(0) is OR of x(1),x(3),x(5), ... --        indx(1) is OR of x(2),x(3), x(6),x(7), x(10),x(11), ... --        indx(2) is OR of x(4),x(5),x(6),x(7), x(12),x(13),x(14(,x(15),... -- -- but it's tricky to code so it works for different word sizes. type vec is array(0 to lgWordSize-1) of std_logic_vector(0 to (wordSize/2)-1); variable fOne: vec; variable anyOne: std_logic_vector(0 to wordSize-1); begin     -- fOne(0)(j) is OR of first j bits in x1,x3,x5,...     -- fOne(1)(j) is OR of first j bits in x2,x3, x6,x7, x10,x11,...     -- fOne(2)(j) is OR of first j bits in x4,x5,x6,x7, x12,x13,x14,x15,...     for i in 0 to lgWordSize-1 loop         for j in 0 to (wordSize/(2**(i+1)))-1 loop                        for h in 0 to (2**i)-1 loop                 if j = 0 and h = 0 then                     fOne(i)(0) := x(2**i);                 else                     fOne(i)((2**i)*j+h) := fOne(i)((2**i)*j+h-1) or                                            x(((2**i)*(2*j+1))+h);                 end if;             end loop;         end loop;         indx(i) := fOne(i)((wordSize/2)-1);     end loop;     anyOne(0) := x(0);     for i in 1 to wordSize-1 loop         anyOne(i) := anyOne(i-1) or x(i);     end loop;     errFlag := not anyOne(wordSize-1); end procedure encode; function firstOne(x: std_logic_vector(0 to wordSize-1))                         return std_logic_vector is -- Returns the index of the first 1 in bit string x. -- If there are no 1's in x, the value returned has a -- 1 in the high order bit. variable allZero: std_logic_vector(0 to wordSize-1); variable fOne: std_logic_vector(0 to wordSize-1); variable rslt: std_logic_vector(lgWordSize downto 0); begin     allZero(0) := not x(0);     fOne(0) := x(0);     for i in 1 to wordSize-1 loop         allZero(i) := (not x(i)) and allZero(i-1);         fOne(i) := x(i) and allZero(i-1);     end loop;     encode(fOne,rslt(lgWordSize-1 downto 0),rslt(lgWordSize));     return rslt; end function firstOne; begin     x <= firstOne(a); end a1;

5. Closing Remarks

Stack Exchange Network

Stack Exchange network consists of 183 Q&A communities including Stack Overflow , the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Q&A for work

Connect and share knowledge within a single location that is structured and easy to search.

Why do we assign our outputs to signals first in VHDL?

I saw in many VHDL codes that data/control outputs are first assigned to signals and then to output ports, and not instantly to the output ports.

I'll give an example:

My question is, why do we not assign some_data instantly to the data_out port? Why does it "have to go through" the signal data_out_sig ? Does this have anything to do with synthesis? Is it common practice?

4 Answers 4

I will tell you a scenario. Suppose you are creating an entity with

2 input ports : A,B 2 output ports : C,D

Suppose the output C is generated from A and B using some logic. And Suppose D is found to be directly related with C. For example:

D = compliment of C

So it is compelling to write in the code: D = not C directly, instead of using a logic expression with and A and B. However VHDL semantics don't allow you to read the output port C and hence you cannot implement such an expression. So what you can do is turn that port into a buffer port. Some people also make use in/out port for this purpose. But that makes thing complex. So a simple solution is to use some local internal signal C_int, and "use" it like the output port inside your code. So that you can implement the logic for C into this internal signal, read it and manipulate with it. Finally assigning this internal signal to the output port, outside all the process blocks, completes the requirement. An example illustration of what is happening inside the circuit:

It's because you couldn't read from ports of type OUT in VHDL.

If the value driving an OUT port was to be read within the design, a signal had to used to hold it, then that signal assigned to the OUT port.

The capability to do so was added in VHDL-2008. However, a huge amount of designs were created before 2008 and before take-up of VHDL-2008 became available in software tools. These designs would therefore use the signal-drives-OUT method.

As an aside, it depends upon your circumstances as an engineer but the option to use VHDL-2008 may well not be available to you. Some companies will require design revisions to be synthesised or simulated by a specific version of software (Quartus, Xilinx ISE, ModelSim etc.) with no changes to the design project settings, so you cannot use VHDL-2008. I have worked in a great many companies that do this, defence companies for example. Moving to a newer version of software introduces an unnecessary risk of unexpected changes that can discredit all the testing and experience gained with that firmware so far, with the time and expense that go with that. So there is a lot of value in writing 'middle of the road' VHDL that will be accepted by the widest range of software tools that you can, rather than using syntax specific to VHDL-2008 or VHDL-2002. The downsides of this are few or none - I'm not aware of anything that you can't do in the earlier versions that vast majority of designs require. As I said, it depends upon your circumstances and is something to consider. For me, I would definitely use signal-drives-OUT. Being completely portable between software tools and versions is valuable to me and one of my priorities.

If the signal from an output port also is read back you have to use the 'buffer' port type.

That by itself would not be a problem but if that 'output' port goes up a hierarchical chain of modules you have to change the output of each model to 'buffer'.

To avoid the hassle it is easiest to use a local variable and in one place assign that to the output.

I prefer to use that technique only for output ports that are also read back but I can image somebody preferring to use it all the time.

• 1 \$\begingroup\$ You can read back from OUT ports in VHDL-2008. So, this is either obsolete practice or a concession to obsolete tools. \$\endgroup\$ –  user16324 Commented Dec 29, 2017 at 19:25

Notice that data_out is defined as an output. That means it can only be written to. However, you cannot read from it.

So you can directly go

data_out <= some_data;

That works fine. But suppose some_data needed to be continuously modified.

For my purposes of these examples, I will assume the data types are integers and not std_logic like in your original post.

I cannot do

data_out <= data_out + 1

because this would require a read prior to adding the one. Since you cannot read from data_out, this would not work.

data_out <= some_data + 1

and this would work, but in doing so, I can no longer manipulate the result in the future because it is now stored in data_out and can no longer be read from.

If I want to manipulate the result in the future, then I have to go

data_out_sig <= some_data + 1; --can continue to reading and modify the result in the future data_out <= data_out_sig;

So you can assign data instantly to the output if you don't need to ever manipulate what is stored in data_out. For example, a conditional branch could decide that the output needs to be a '1' or '0'. You could write this directly to the output without an intermediary.

data_out <= 1;

Your Answer

Sign up or log in, post as a guest.

Required, but never shown

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy .

Not the answer you're looking for? Browse other questions tagged vhdl or ask your own question .

• The Overflow Blog
• The evolution of full stack engineers
• One of the best ways to get value for AI coding tools: generating tests
• Featured on Meta
• Bringing clarity to status tag usage on meta sites
• Join Stack Overflow’s CEO and me for the first Stack IRL Community Event in...

Hot Network Questions

• Engaging students in the beauty of mathematics
• Model reduction in linear regression by stepwise elimination of predictors with "non-significant" coefficients
• using gnu date to set a time and format and subtract
• How to fold or expand the wingtips on Boeing 777?
• Do images have propositional content?
• Remove spaces from the 3rd line onwards in a file on linux
• Colossians 1:16 New World Translation renders τα πάντα as “all other things” but why is this is not shown in their Kingdom Interlinear?
• Fantasy book about humans and gnomes entering one another's worlds
• I want to write a script that simultaneously renders whats on my webcam to a window on my screen and records a video
• About Jesus's reading of Isaiah in the synagogue
• The pronoun in short yes/no answers to rhetorical tag-questions with the generic "you"
• Is there mathematical significance to the LaGuardia floor tiles?
• Are there epistemic vices?
• What is the working justification of this circuit?
• Is the highlighted part false?
• How resiliant is a private key passphase to brute force attacks?
• Paragraph indents dissapeared suddenly
• Analog story - US provides food machines to other nations, with hidden feature
• Why does each leg of my 240V outlet measure 125V to ground, but 217V across the hot wires?
• Part bound and part living thing
• Mistake on car insurance policy about use of car (commuting/social)
• Torah service on shabbat with no kohanim and not enough yisraelim
• Why wasn't Randall Stevens caught?
• What is the purpose of long plastic sleeve tubes around connections in appliances?

• Stack Overflow for Teams Where developers & technologists share private knowledge with coworkers
• Advertising & Talent Reach devs & technologists worldwide about your product, service or employer brand
• OverflowAI GenAI features for Teams
• OverflowAPI Train & fine-tune LLMs
• Labs The future of collective knowledge sharing
• About the company Visit the blog

Collectives™ on Stack Overflow

Find centralized, trusted content and collaborate around the technologies you use most.

Q&A for work

Connect and share knowledge within a single location that is structured and easy to search.

Get early access and see previews of new features.

Signal assignment method

I am new to VHDL and have had some difficulty in performing the assignment of two different values to the same signal inside a process. For example,

Note that VALUE is an output dependent on the values assigned to OUTPUT0, OUTPUT1, OUTPUT2 .

From what I understand in a process is that the last assignment to the same signal is always applied. What I am trying to do is apply two different sets of values to one set of inputs, map the output and it be done sequentially. I have tried separate processes tied to the same clock, a FSM to attempt to move sequentially and so on. At this point I have exhausted my knowledge of things to try.

My question is: What would be the best way to sequentially assign two values to one input and map its output in order?

As per Brian's suggestion on the state machine I had went ahead and implemented one again and found my error and fixed it. This gave the sequential assignment I was looking for.

I was reading 2 addresses from one instance of 32x1 distributed RAM which is the reason for a sequential assignment. Apologies for not providing the best example. Below is my final implementation:

• 1 Can you clarify "apply two different sets of values to one set of inputs?" –  Travis Commented Nov 24, 2020 at 17:55
• Processes resume and suspend in wait statements (implicit wait on the process sensitivity list here), Signal updates are scheduled in a projected output waveform queue and don't occur when processes are executing. There's only one entry there for each simulation time earlier updates will be overwritten by later assignments as here. VHDL descriptions are taken as formal proofs by synthesis. The "best way" invites opinion based on a code fragment. Provide information on X, Y and VALUE, a minimal reproducible example would help. The question may also be too narrow there may be 'better' hardware solutions. –  user1155120 Commented Nov 24, 2020 at 19:50

The signals should be driven from the same process : multiple drivers would interfere with each other..

See Is process in VHDL reentrant? on signal assignment semantics.

now you can see there is need for some delay (even just 2 delta cycles, if the logic calculating VALUE is just a simple signal assignment) between the X and LED0 assignments.

You were on the right lines with a state machine but you didn't say anything about how it failed. Worth adding that to the Q to get a fuller answer.

Meanwhile there is a simple way to add delay :

• Thank you for your answer! And specifically the state machine as well the link. I implemented a state machine again and found an error in it and fixed it. By doing the state machine my two assignments were made sequentially. –  Lotley Commented Nov 24, 2020 at 23:26

Your Answer

Reminder: Answers generated by artificial intelligence tools are not allowed on Stack Overflow. Learn more

Sign up or log in

Post as a guest.

Required, but never shown

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy .

Not the answer you're looking for? Browse other questions tagged vhdl or ask your own question .

• The Overflow Blog
• The evolution of full stack engineers
• One of the best ways to get value for AI coding tools: generating tests
• Featured on Meta
• Bringing clarity to status tag usage on meta sites
• Join Stack Overflow’s CEO and me for the first Stack IRL Community Event in...
• Feedback requested: How do you use tag hover descriptions for curating and do...
• Staging Ground Reviewer Motivation
• What does a new user need in a homepage experience on Stack Overflow?

Hot Network Questions

• What is the purpose of long plastic sleeve tubes around connections in appliances?
• How solid is the claim that Alfred Nobel founded the Nobel Prize specifically because of his invention of dynamite?
• Is the highlighted part false?
• Guesstimate a multiple choice exam
• Practice test paper answers all seem incorrect, but provider insists they are ... what am i missing?
• Why does ATSAM3X8E have two separate registers for setting and clearing bits?
• Please help me identify my Dad's bike collection (80's-2000's)
• Why do "modern" languages not provide argv and exit code in main?
• Why wasn't Randall Stevens caught?
• About Jesus's reading of Isaiah in the synagogue
• What is the least number of colours Peter could use to color the 3x3 square?
• Can we use "day and night time" instead of "day and night"?
• Can a V22 Osprey operate with only one propeller?
• Part bound and part living thing
• Correct anonymization of submission using Latex
• Did the heavenly Temple have a separation of the two inner rooms?
• Is the white man at the other side of the Joliba river a historically identifiable person?
• Where Does Rashi Mention the Streets of Venice?
• The quest for a Wiki-less Game
• Wrong explanation for why "electron can't exist in the nucleus"?
• Why public key is taken in private key in Kyber KEM?
• When should I put a biasing resistor - op-amps
• How to fold or expand the wingtips on Boeing 777?
• Big Transition of Binary Counting in perspective of IEEE754 floating point