concurrent assignment to non net

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Concurrent assignment to a non-net '_' is not permitted

I’m getting the error:

What am I doing wrong?

March 2, 2023 at 11:55 am

In the ex1 module, you are trying to make a concurrent assignment to a non-net variable ‘a’ and ‘b’. Non-net variables are not allowed to be used in concurrent assignments. You should use ‘wire’ instead of ‘reg’ for ‘a’ and ‘b’. Also, the ternary operator should be modified to assign the value of ‘c’ instead of ‘a’ when the condition is true.

Here is the corrected code:

Comments are closed.

Verilog Tips 1:TestBench编写注意事项【concurrent assignment to a non-net ‘xxxx‘ is not permitted】解决

对于模块中的输出来说即，不能以 TestBench中的 reg 型赋值给被测模块作为输出的 wire 型；同，不能以 TestBench中的 reg 型赋值给被测模块作为输出的 reg 型；只能以TestBench中的 wire 型赋值给被测模块作为输出的 wire 型，对于输入来说用 reg 可行。

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Verilog wire instead of reg output interface for continuous assignment #6

Risto97 commented Jul 18, 2019

Modules such as ccat.v, cast_dout.v, sieve.v are using continous assignment on output reg signals. eg.

Yosys reports warning:

Vivado reports error:

bogdanvuk commented Sep 21, 2020

Thanks Risto, this has been fixed in the new version.

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[Solved] Concurrent assignment to a non-net is not permitted. Verilog

Thread starter Alexander Smyatskikh
Start date May 26, 2023

Alexander Smyatskikh

May 26, 2023

Alexander Smyatskikh Asks: Concurrent assignment to a non-net is not permitted. Verilog Concurrent assignment to a non-net is not permitted. Verilogic. What am i doing wrong? Here are mistakes i got Code: ERROR EX3805 : concurrent assignment to a non-net 'LED1' is not permitted(C:/Users/smyat/Documents/Laba4/src/TOP.v:19) ERROR EX3805 : concurrent assignment to a non-net 'LED2' is not permitted(C:/Users/smyat/Documents/Laba4/src/TOP.v:21) ERROR EX3805 : concurrent assignment to a non-net 'LED3' is not permitted(C:/Users/smyat/Documents/Laba4/src/TOP.v:23) ERROR EX3805 : concurrent assignment to a non-net 'LED4' is not permitted(C:/Users/smyat/Documents/Laba4/src/TOP.v:25) ERROR EX3805 : concurrent assignment to a non-net 'LED5' is not permitted(C:/Users/smyat/Documents/Laba4/src/TOP.v:27) ERROR EX3928 : module 'k' is ignored due to previous errors(C:/Users/smyat/Documents/Laba4/src/TOP.v:53) Code: module k( input btn1, input btn2, input btn3, input btn4, input btn5, output reg LED1, output reg LED2, output reg LED3, output reg LED4, output reg LED5 ); assign LED1 = !btn1; assign LED2 = !btn2; assign LED3 = !btn3; assign LED4 = !btn4; assign LED5 = !btn5; //always @ ( btn1, btn2, btn3, btn4, btn5, LED1, LED2, LED3, LED4, LED5) //begin //if (btn1) // LED1 = 1; //if (btn2) // LED2 = 1; //if (btn3) // LED3 = 1; //if (btn4) // LED4 = 1; //if (btn5) // LED5 = 1; //end endmodule I tried to restart it on another computer, and it works. Also i delete and create again project, it doesn't help me.

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instantiation problem with sequential blocks in verilog

Thread starter naveenkumarmadala
Start date Mar 16, 2015
Mar 16, 2015

naveenkumarmadala

Newbie level 3.

Code Verilog - ]
	mnk(clk,rst,in,out); input clk,rst; input [7:0]in; output reg[7:0]out; wire [7:0]w1; wire [7:0]w2; wire [7:0]w3; wire [7:0]w4; wire [7:0]w5; wire [7:0]w6; wire [7:0]w7; always@(posedge clk or rst) begin if(rst) begin out[7:0]<=8'b0; end else begin ca90 dut0(clk,rst,in,w1); ca90 dut1(clk,rst,w1,w2); ca90 dut2(clk,rst,w2,w3); ca90 dut3(clk,rst,w3,w4); ca90 dut4(clk,rst,w4,w5); ca90 dut5(clk,rst,w5,w6); ca90 dut6(clk,rst,w6,w7); ca90 dut7(clk,rst,w7,out); end end endmodule module ca90(clk,rst,s,q); input clk,rst; input [7:0]s; output reg[7:0]q; always@(posedge clk or rst) begin if(rst) begin q[7:0] =8'b0; end else begin q[0]=0^s[1]; q[1]=s[0]^s[2]; q[2]=s[1]^s[3]; q[3]=s[2]^s[4]; q[4]=s[3]^s[5]; q[5]=s[4]^s[6]; q[6]=s[5]^s[7]; q[7]=s[6]^0; end end endmodule

Code Verilog - ]

mnk(clk,rst,in,out); input clk,rst; input [7:0]in; output reg[7:0]out; wire [7:0]w1; wire [7:0]w2; wire [7:0]w3; wire [7:0]w4; wire [7:0]w5; wire [7:0]w6; wire [7:0]w7; always@(posedge clk or rst) begin if(rst) begin out[7:0]<=8'b0; end else begin ca90 dut0(clk,rst,in,w1); ca90 dut1(clk,rst,w1,w2); ca90 dut2(clk,rst,w2,w3); ca90 dut3(clk,rst,w3,w4); ca90 dut4(clk,rst,w4,w5); ca90 dut5(clk,rst,w5,w6); ca90 dut6(clk,rst,w6,w7); ca90 dut7(clk,rst,w7,out); end end endmodule module ca90(clk,rst,s,q); input clk,rst; input [7:0]s; output reg[7:0]q; always@(posedge clk or rst) begin if(rst) begin q[7:0] =8'b0; end else begin q[0]=0^s[1]; q[1]=s[0]^s[2]; q[2]=s[1]^s[3]; q[3]=s[2]^s[4]; q[4]=s[3]^s[5]; q[5]=s[4]^s[6]; q[6]=s[5]^s[7]; q[7]=s[6]^0; end end endmodule

Super Moderator

TPG means? Forum rules say don't use technical abbrevations that aren't universally known. I believe that you get unexpected results, but why do you think to solve the problem by instantiating modules in sequential code? Apart from being no legal Verilog syntax, what's the idea behind it?

Verilog isn't a software language, it is a hardware description language. Constructs like "calling" a DUT aren't allowed in sequential blocks. The entire always block needs to be removed and replaced with just the ca90 dut0...ca90 dut7 lines. From what I can tell you want to create multiple copies of the dut with each output feeding the next input. Except you think that Verilog works like a software language and you can "call" your dut in the sequential code like you would with a subroutine call in something like C.

Code Verilog - ]
	mnk_kr( input clk,rst, input [7:0]in, output reg[7:0]out); wire [7:0]w1; wire [7:0]w2; wire [7:0]w3; wire [7:0]w4; wire [7:0]w5; wire [7:0]w6; wire [7:0]w7; ca90 dut0(clk,rst,in,w1); ca90 dut1(clk,rst,w1,w2); ca90 dut2(clk,rst,w2,w3); ca90 dut3(clk,rst,w3,w4); ca90 dut4(clk,rst,w4,w5); ca90 dut5(clk,rst,w5,w6); ca90 dut6(clk,rst,w6,w7); ca90 dut7(clk,rst,w7,out); endmodule module ca90( input clk,rst, input [7:0]s, output reg[7:0]q); always@(posedge clk , posedge rst) begin if(rst) begin q[7:0] =8'b0; end else begin q[0]=0^s[1]; q[1]=s[0]^s[2]; q[2]=s[1]^s[3]; q[3]=s[2]^s[4]; q[4]=s[3]^s[5]; q[5]=s[4]^s[6]; q[6]=s[5]^s[7]; q[7]=s[6]^0; end end endmodule

Code Verilog - ]

mnk_kr( input clk,rst, input [7:0]in, output reg[7:0]out); wire [7:0]w1; wire [7:0]w2; wire [7:0]w3; wire [7:0]w4; wire [7:0]w5; wire [7:0]w6; wire [7:0]w7; ca90 dut0(clk,rst,in,w1); ca90 dut1(clk,rst,w1,w2); ca90 dut2(clk,rst,w2,w3); ca90 dut3(clk,rst,w3,w4); ca90 dut4(clk,rst,w4,w5); ca90 dut5(clk,rst,w5,w6); ca90 dut6(clk,rst,w6,w7); ca90 dut7(clk,rst,w7,out); endmodule module ca90( input clk,rst, input [7:0]s, output reg[7:0]q); always@(posedge clk , posedge rst) begin if(rst) begin q[7:0] =8'b0; end else begin q[0]=0^s[1]; q[1]=s[0]^s[2]; q[2]=s[1]^s[3]; q[3]=s[2]^s[4]; q[4]=s[3]^s[5]; q[5]=s[4]^s[6]; q[6]=s[5]^s[7]; q[7]=s[6]^0; end end endmodule

Code Verilog - ]
	begin clk = 0; forever begin #50 clk = !clk; end end

Everything looks O.K., except for the test bench. - not operating rst - generating no input data - placing the clk generation in initial block

FvM said: - placing the clk generation in initial block Click to expand...

Mar 17, 2015

Code Verilog - ]
	mnk_kr_tb; reg clk; reg rst; reg [7:0] in; wire [7:0] out; mnk_kr uut ( .clk(clk), .rst(rst), .in(in), .out(out) ); initial begin rst = 1; in = 8'b10100110; #100; rst = 0; in = 8'b10100110; end initial begin clk <= 0; forever begin #5 clk <= ~clk; end end endmodule

i sent whatever i have written,if you have changed anything in test bench please send me the code and here i am attaching my simulation results done in Xilix.please tell me where i should change my code. Click to expand...

The testbench is fine, I don't see a "xxxxxxxx" problem. - - - Updated - - - I'm not using Xilinx, the results look like mnk_kr hasn't been compiled to the design, there should be a warning.

Code Verilog - ]
	mnk_kr( input clk,rst, input [7:0]in, output reg[7:0]out); ca90 dut7(clk,rst,w7,out);

Code Verilog - ]
	mnk_kr( input clk,rst, input [7:0]in, output [7:0]out);

which results in a problem in elaboration, since you can't connect an output of a instance to an output port using reg. You need to use wire... Click to expand...

I see you are referring to 23.3.3.2 Port connection rules for variables in 1800-2012. The problem the OP is having seems to be a partial implementation of that rule in ISE, whereas Vivado just declares it an error (no support for SV, didn't try it with the undocumented -sv switch).

It's O.K. that the Vivado simulator enforces classical Verilog rules with no SV support enabled, just wasn't aware of the conflict as my toolchain ignored it. The error message is however clear enough to fix the problem fastly. I don't believe that the said "xxxxxxxx" problem is related to net versus wire type, rather expect a trivial explanation as supposed.

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Error: HDL-Complier-661 Non-net port cannot be mode of input

I'm trying to develop a Verilog code for right shifting as a part of Floating Point ALU. I'm getting the following error in line 7:

Error: HDL-Complier-661 .... Non net port cannot be mode of input

Please tell me what my error is and provide me with corrected code.

3 Answers 3

Verilog does not allow input ports declared as a variable with a data type (SystemVerilog does).You can remove that line. I also suggest using a simpler form of port declarations that only mentions each port name once instead of up to three times (called ANSI style in the IEEE LRM)

\$\begingroup\$ This worked . Note that we have to use comas, instead if semicolons. module right_shifter( input [3:0] small_mant, input [2:0] shift_amt, output reg [5:0] shifted_mant ); \$\endgroup\$ – Abhishek Chunduri Commented May 7, 2020 at 10:26

You've declared your port as input [3:0] small_mant; - this means you are declaring an input to the module, which must be of a net type (a.k.a. a wire ).

However you then re-declare your input port as reg [3:0] small_mant; which is a variable data type ( reg ), and therefore not a net type.

You cannot, and in fact never need to, declare an input as a reg , so simply remove that line.

The corrected code :-

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Verilog error "continuous assignment output must be a net"

I am working on a an assignment where I have to synthesize my Verilog code. I wrote the code and compiled and simulated, and everything worked fine. When I went to synthesize, the design compiler gave me an error in one of my modules. This module represents a simple 8-bit shift register with a data buffer. When I synthesize, it gives me an error:

continuous assignment output buffer must be a net

I don't know what this message is stating.

The message is telling you that the signal you are assigning to with the continuous assignment (using the assign keyword) must be a net type variable, such as a wire . But, you declared buffer as a reg type variable. This is illegal, and your simulator should have at least warned you about this before you got to synthesis. The simulators I use gave me compile errors.

You can simply delete this line:

Inside the 1st always block, you already assign buffer[0] to shift_in implicitly in the line:

After you fix that, you still have a problem. The 2nd always block is odd for a number of reasons. The syntax is legal, but it does not adhere to good synthesis coding practices. Perhaps you meant to combine the 2 always blocks into 1:

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Verilog Tips 1:TestBench编写注意事项【concurrent assignment to a non-net ‘xxxx
Verilog: Prohibition of simultaneous assignment to a non-net
Verilog Tips 1:TestBench编写注意事项【concurrent assignment to a non-net ‘xxxx
vivado仿真报错：concurrent assignment to a non-net led is not permitted-CSDN博客
Verilog Tips 1:TestBench编写注意事项【concurrent assignment to a non-net ‘xxxx
Verilog Tips 1:TestBench编写注意事项【concurrent assignment to a non-net ‘xxxx

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COMMENTS

What is "concurrent assignment to a non-net <port_name> is not
Your tool considers a reg to be a "non-net". In your testbench, change: reg [31:0]inst_out; to: wire [31:0]inst_out; You should do the same for any other outputs. Share. Follow ... Concurrent assignment to a non-net is not permitted. 0. Illegal output or inout port connection for port. 1.
Concurrent assignment to a non-net '_' is not permitted
The trailing comma in a port list is illegal. Change: output wire c, to: output wire c. It is illegal to assign a value to an input port inside a module. This is illegal: a=1'b1. Assuming it was a typo to use a there, and you really meant to type c, you should change: assign c=(a>b)?(a=1'b1):(c=1'b0);
Concurrent assignment to a non-net is not permitted
Concurrent assignment to a non-net is not permitted. Ask Question Asked 6 years, 5 months ago. Modified 2 years, 5 months ago. Viewed 29k times 1 I'm making module that make results according to cmd using 4 32-bit adder. if cmd is 0, dout0 = a0+b0, and other dout is zero if cmd is 1, dout1 = a1+b1 and other dout is zero. if cmd is 2 or 3 ...
help me solve concurrent assignment error in verilog for the code given
Module puts need to be connected to a net-type (ex wire). However a wire cannot be assigned in a procedural code (ex always block). So you need to think how to assign some bits to from a module and other from procedural. \$\endgroup\$
vivado仿真报错：concurrent assignment to a non-net out is not permitted
vivado仿真报错：concurrent assignment to a non-net out is not permitted. procedural assignment to a non -register F is not permitted "表示在代码的第31行，对一个非寄存器类型的信号F进行了过程赋值操作，这是不允许的。. 中的介绍，过程赋值使用的是非阻塞赋值"<= "，而非阻塞赋值只能 ...
verilog
Target tr26 of concurrent assignment or output port connection should be a net type., respectively. When the target is assigned as a wire and not as a reg, then it works fine. ... Error: HDL-Complier-661 Non-net port cannot be mode of input. 3. Error: HDL Compiler : 1660 : Procedural assignment to a non-register big_mant is not permitted, left ...
Concurrent assignment or output port connection should be a net type
You cannot drive a reg type via a continuous assignment (only a wire may be driven in this way).. If this is just modelling combinatorial logic, you could use a combinatorial always block: always @* begin mem[in_d0_] = in_d1_; end
Verilog real number assignment error in Vivado
the continuous assign you are using is only allowed on "net" types (section 6.1.2 of 1364.2001). Real is a reg type (section 3.9 of the same) so I think Vivado is right not to allow it. Try always @* c_real = a_real \+ b_real; which for all practical purposes implements the same logic.
Concurrent assignment to a non-net '_' is not permitted
In the ex1 module, you are trying to make a concurrent assignment to a non-net variable 'a' and 'b'. Non-net variables are not allowed to be used in concurrent assignments. You should use 'wire' instead of 'reg' for 'a' and 'b'. Also, the ternary operator should be modified to assign the value of 'c' instead of 'a ...
Verilog Tips 1:TestBench编写注意事项【concurrent assignment to a non-net 'xxxx
文章浏览阅读2.3w次，点赞18次，收藏57次。一个案例：待测试模块输入输出为：TestBench测试文件为：一仿真，报错 concurrent assignment to a non-net 'xxxx' is not permitted原因分析：对于待测试模块的输出 "dout_7888"，在编写测试文件的时候，不能将与之交联的"dout_7888"定义为 reg 型，须改为 wire 型。
Verilog wire instead of reg output interface for continuous assignment
Modules such as ccat.v, cast_dout.v, sieve.v are using continous assignment on output reg signals. eg. module abc( output reg dout_valid); // should be output wire assign dout_valid = 10; endmodule ... reg '\dout_s' is assigned in a continuous assignment at ... Vivado reports error: [Synth 8-1852] concurrent assignment to a non-net dout_s is ...
[Solved] Concurrent assignment to a non-net is not ...
The session number 11907571 is a random number and usernames also differ so grepping can ignore the numbers and usernames, only need to check the string like: **"Started Session *** of user ***". And need to parse the line and grep the date + time, and username then insert it into the MySQL database.
xilinx
ERROR:HDLCompiler:329 - "tb.v" Line 29. Concurrent assignment to a non-net a is not permitted . ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed ... Target <tr26> of concurrent assignment or output port connection should be a net type. 0. How to solve ERROR Xst:528 in ISE? 0. Verilog Include ...
instantiation problem with sequential blocks in verilog
Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-529] concurrent assignment to a non-net out is not permitted [mnk_kr_tb.v:21] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
Verilog 常见 Error
ERROR: concurrent assignment to a non-net 'dout_x' is not permitted . 错误提示：不允许并发分配给非网线"xxx" 错误原因：模块例化后之间的连接应采用"wire"类型，错误使用"reg" ERROR: if-condition does not match any sensitivity list edge . 错误提示：如果条件与任何敏感度列表边缘都 ...
Error: HDL-Complier-661 Non-net port cannot be mode of input
You've declared your port as input [3:0] small_mant; - this means you are declaring an input to the module, which must be of a net type (a.k.a. a wire).. However you then re-declare your input port as reg [3:0] small_mant; which is a variable data type (reg), and therefore not a net type.. You cannot, and in fact never need to, declare an input as a reg, so simply remove that line.
Why does Xilinx throw this error? [Synth 8-2576] procedural assignment
ESP32 is a series of low cost, low power system on a chip microcontrollers with integrated Wi-Fi and dual-mode Bluetooth. The ESP32 series employs either a Tensilica Xtensa LX6, Xtensa LX7 or a RiscV processor, and both dual-core and single-core variations are available.
Verilog error "continuous assignment output must be a net"
This module represents a simple 8-bit shift register with a data buffer. When I synthesize, it gives me an error: continuous assignment output buffer must be a net. I don't know what this message is stating. module shiftReg(output shift_out, output reg [7:0] data_buff, input shift_write, clk, shift_in, input [7:0] data); reg [7:0] buffer;

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Verilog wire instead of reg output interface for continuous assignment #6

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[Solved] Concurrent assignment to a non-net is not permitted. Verilog

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Error: HDL-Complier-661 Non-net port cannot be mode of input

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