common emitter configuration experiment

BJT Common Emitter Characteristics            

Bjt common emitter - input characteristics.

• Initially set rheostat R h1 = 1 Ω and rheostat R h2 = 1 Ω
• Set the Collector-Emitter Voltage(V CE ) to 1 V by adjusting the rheostat R h2
• Base Emitter Voltage(V BE ) is varied by adjusting the rheostat R h1 .
• Note the reading of Base current(I B )in micro Ampere.
• Click on 'Plot' to plot the I-V characteristics of Common-Emitter configuration. A graph is drawn with V BE along X-axis and I B along Y-axis.
• Click on 'Clear' button to take another sets of readings
• Now set the Collector-Emitter Voltage(V CE ) to 2 V, 3 V, 4 V

BJT Common Emitter - Output Characteristics

• Set the Base current(I B )15 uA by adjusting the rheostat R h1
• Vary the Collector-Emitter Voltage(V CE )is varied by adjusting the rheostat R h2 .
• Note the reading of Collector current(I C ).
• Click on 'Plot' to plot the I-V characteristics of Common-Emitter configuration. A graph is drawn with V CE along X-axis and I C along Y-axis.
• Now set the Base Current(I B ) to 20 uA

Common Emitter Connection (or CE Configuration)

Definition : The configuration in which the emitter is connected between the collector and base is known as a common emitter configuration. The input circuit is connected between emitter and base, and the output circuit is taken from the collector and emitter. Thus, the emitter is common to both the input and the output circuit, and hence the name is the common emitter configuration. The common emitter arrangement for NPN and PNP transistor is shown in the figure below.

Base Current Amplification Factor (β)

The base current amplification factor is defined as the ratio of the output and input current in a common emitter configuration. In common emitter amplification, the output current is the collector current I C, and the input current is the base current I B .

In other words, the ratio of change in collector current with respect to base current is known as the base amplification factor. It is represented by β (beta).

Relation Between Current Amplification Factor (α) & Base Amplification Factor (β)

The relation between Β and α can be derived as

Substituting the value of ΔI E in equation (1), we get,

Collector Current

In CE configuration, the input current I B and the output current I C are related by the equation shown below.

If the base current is open (i.e., I B = 0). The collector current is current to the emitter, and this current is abbreviated as I CEO that means collector- emitter current with the base open.

Substitute the value ΔI B in equations (1), we get,

Characteristics of Common emitter (CE) Configuration

The characteristic of the common emitter transistor circuit is shown in the figure below. The base to emitter voltage varies by adjusting the potentiometer R 1 . And the collector to emitter voltage varied by adjusting the potentiometer R 2 . For the various setting, the current and voltage are taken from the milliammeters and voltmeter. On the basis of these readings, the input and output curve plotted on the curve.

Input Characteristic Curve

The curve plotted between base current I B and the base-emitter voltage V EB is called Input characteristics curve. For drawing the input characteristic the reading of base currents is taken through the ammeter on emitter voltage V BE at constant collector-emitter current. The curve for different value of collector-base current is shown in the figure below.

The curve for common base configuration is similar to a forward diode characteristic. The base current I B increases with the increases in the emitter-base voltage V BE . Thus the input resistance of the CE configuration is comparatively higher that of CB configuration.

The effect of CE does not cause large deviation on the curves, and hence the effect of a change in V CE on the input characteristic is ignored.

Input Resistance: The ratio of change in base-emitter voltage V BE to the change in base current ∆I B at constant collector-emitter voltage V CE is known as input resistance, i.e.,

Output Characteristic

In CE configuration the curve draws between collector current I C and collector-emitter voltage V CE at a constant base current I B is called output characteristic. The characteristic curve for the typical NPN transistor in CE configuration is shown in the figure below.

In the active region, the collector current increases slightly as collector-emitter V CE current increases. The slope of the curve is quite more than the output characteristic of CB configuration. The output resistance of the common base connection is more than that of CE connection.

The value of the collector current I C increases with the increase in V CE at constant voltage I B , the value β of also increases.

When the V CE falls, the I C also decreases rapidly. The collector-base junction of the transistor always in forward bias and work saturate. In the saturation region, the collector current becomes independent and free from the input current I B

In the active region I C = βI B , a small current I C is not zero, and it is equal to reverse leakage current I CEO .

Output Resistance: The ratio of the variation in collector-emitter voltage to the collector-emitter current is known at collector currents at a constant base current I B is called output resistance r o .

The value of output resistance of CE configuration is more than that of CB

Related terms:

• Common Base Connection (CB Configuration)
• Common Collector Connection (or CC Configuration)
• Common Emitter Amplifier
• Scott-T Transformer Connection
• Difference Between Star and Delta Connection

7 thoughts on “Common Emitter Connection (or CE Configuration)”

nice article and good representation

Nice material for gaining knowledge.

The content is quite beneficial!!

Easy to understand

A short and clear description 😍 This part of electronics was really difficult for me, but this website helped me so much

Nice answer

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• Semiconductors

Bipolar Junction Transistors

• Introduction to Bipolar Junction Transistors (BJT)
• The Bipolar Junction Transistor (BJT) as a Switch
• Meter Check of a Transistor (BJT)
• Active-mode Operation (BJT)
• The Common-collector Amplifier
• The Common-base Amplifier
• The Cascode Amplifier
• Biasing Techniques (BJT)
• Transistor Biasing Calculations
• Input and Output Coupling
• Amplifier Impedances
• Current Mirror BJTs
• Transistor Ratings and Packages (BJT)

At the beginning of this chapter, it illustrates how transistors could be used as switches, operating in either their “ saturation” or “cutoff” modes . In the last section, we saw how transistors behave within their “active” modes , between the far limits of saturation and cutoff. Because transistors are able to control current in an analog fashion, they find use as amplifiers for analog signals.

Transistor as a Simple Switch

Common-Emitter One of the simpler transistor amplifier circuits to study previously illustrated the transistor’s switching ability.

NPN transistor as a simple switch.

It is called the common-emitter configuration because (ignoring the power supply battery) both the signal source and the load share the emitter lead as a common connection point shown in the figure below. This is not the only way in which a transistor may be used as an amplifier, as we will see in later sections of this chapter.

Common-emitter amplifier: The input and output signals both share a connection to the emitter.

Before, a small solar cell current saturated a transistor, illuminating a lamp. Knowing now that transistors can “throttle” their collector currents according to the amount of base current supplied by an input signal source, we should see that the brightness of the lamp in this circuit is controllable by the solar cell’s light exposure . When there is just a little light shone on the solar cell, the lamp will glow dimly. The lamp’s brightness will steadily increase as more light falls on the solar cell.

Suppose that we were interested in using the solar cell as a light intensity instrument. We want to measure the intensity of incident light with the solar cell by using its output current to drive a meter movement. It is possible to directly connect a meter movement to a solar cell for this purpose. The simplest light-exposure meters for photography work are designed like this.

High intensity light directly drives light meter.

Although this approach might work for moderate light intensity measurements, it would not work as well for low light intensity measurements. Because the solar cell has to supply the meter movement’s power needs, the system is necessarily limited in its sensitivity. Supposing that our need here is to measure very low-level light intensities, we are pressed to find another solution.

Transistor as an Amplifier

Perhaps the most direct solution to this measurement problem is to use a transistor to amplify the solar cell’s current so that more meter deflection may be obtained for less incident light.

Cell current must be amplified for low intensity light.

Current through the meter movement in this circuit will be β times the solar cell current. With a transistor β of 100, this represents a substantial increase in measurement sensitivity. It is prudent to point out that the additional power to move the meter needle comes from the battery on the far right of the circuit, not the solar cell itself. All the solar cell’s current does is control battery current to the meter to provide a greater meter reading than the solar cell could provide unaided.

Because the transistor is a current-regulating device, and because meter movement indications are based on the current through the moving coil, meter indication in this circuit should depend only on the current from the solar cell, not on the amount of voltage provided by the battery. This means the accuracy of the circuit will be independent of battery condition, a significant feature! All that is required of the battery is a certain minimum voltage and current output ability to drive the meter full-scale.

Voltage Output due to Current Through a Load Resistor

Another way in which the common-emitter configuration may be used is to produce an output voltage derived from the input signal, rather than the specific output current . Let’s replace the meter movement with a plain resistor and measure voltage between collector and emitter.

Common emitter amplifier develops voltage output due to the current through the load resistor.

With the solar cell darkened (no current), the transistor will be in cutoff mode and behave as an open switch between collector and emitter. This will produce a maximum voltage drop between collector and emitter for maximum V output , equal to the full voltage of the battery.

At full power (maximum light exposure), the solar cell will drive the transistor into saturation mode, making it behave like a closed switch between collector and emitter. The result will be a minimum voltage drop between collector and emitter, or almost zero output voltage. In actuality, a saturated transistor can never achieve zero voltage drop between collector and emitter because of the two PN junctions through which collector current must travel. However, this “collector-emitter saturation voltage” will be fairly low, around several tenths of a volt, depending on the specific transistor used.

For light exposure levels somewhere between zero and maximum solar cell output, the transistor will be in its active mode, and the output voltage will be somewhere between zero and full battery voltage. An important quality to note here about the common-emitter configuration is that the output voltage is inverted with respect to the input signal. That is, the output voltage decreases as the input signal increases. For this reason, the common-emitter amplifier configuration is referred to as an inverting amplifier.

A quick SPICE simulation (figure below) of the circuit in the figure below will verify our qualitative conclusions about this amplifier circuit.

Common emitter schematic with node numbers and corresponding SPICE netlist.

Common emitter: collector voltage output vs base current input.

At the beginning of the simulation in the figure above where the current source (solar cell) is outputting zero current, the transistor is in cutoff mode and the full 15 volts from the battery is shown at the amplifier output (between nodes 2 and 0). As the solar cell’s current begins to increase, the output voltage proportionally decreases, until the transistor reaches saturation at 30 µA of base current (3 mA of collector current). Notice how the output voltage trace on the graph is perfectly linear (1-volt steps from 15 volts to 1 volt) until the point of saturation, where it never quite reaches zero. This is the effect mentioned earlier, where a saturated transistor can never achieve exactly zero voltage drop between collector and emitter due to internal junction effects. What we do see is a sharp output voltage decrease from 1 volt to 0.2261 volts as the input current increases from 28 µA to 30 µA, and then a continuing decrease in output voltage from then on (albeit in progressively smaller steps). The lowest the output voltage ever gets in this simulation is 0.1299 volts, asymptotically approaching zero.

Transistor as an AC Amplifier

So far, we’ve seen the transistor used as an amplifier for DC signals. In the solar cell light meter example, we were interested in amplifying the DC output of the solar cell to drive a DC meter movement, or to produce a DC output voltage. However, this is not the only way in which a transistor may be employed as an amplifier. Often an AC amplifier for amplifying alternating current and voltage signals is desired. One common application of this is in audio electronics (radios, televisions, and public-address systems). Earlier, we saw an example of the audio output of a tuning fork activating a transistor switch. Let’s see if we can modify that circuit to send power to a speaker rather than to a lamp in the figure below.

Transistor switch activated by audio.

In the original circuit, a full-wave bridge rectifier was used to convert the microphone’s AC output signal into a DC voltage to drive the input of the transistor. All we cared about here was turning the lamp on with a sound signal from the microphone, and this arrangement sufficed for that purpose. But now we want to reproduce the AC signal and drive a speaker. This means we cannot rectify the microphone’s output anymore, because we need an undistorted AC signal to drive the transistor, remove the bridge rectifier and replace the lamp with a speaker:

Common emitter amplifier drives speaker with audio frequency signal.

Since the microphone may produce voltages exceeding the forward voltage drop of the base-emitter PN (diode) junction, a resistor must be placed in series with the microphone. Simulate the circuit with SPICE. The netlist is included in (Figure below)

SPICE version of common emitter audio amplifier.

Signal clipped at collector due to lack of DC base bias.

The simulation plots both the input voltage (an AC signal of 1.5-volt peak amplitude and 2000 Hz frequency) and the current through the 15-volt battery, which is the same as the current through the speaker. What we see here is a full AC sine wave alternating in both positive and negative directions and a half-wave output current waveform that only pulses in one direction. If we were driving a speaker with this waveform, the sound produced would be distorted.

What’s wrong with the circuit? Why won’t it faithfully reproduce the entire AC waveform from the microphone? The answer to this question is found by close inspection of the transistor diode current source model in the figure below.

The model shows that base current flows in one direction.

Collector current is controlled or regulated, through the constant-current mechanism according to the pace set by the current through the base-emitter diode. Note that both current paths through the transistor are monodirectional: one way only! Despite our intent to use the transistor to amplify an AC signal, it is essentially a DC device, capable of handling currents in a single direction. We may apply an AC voltage input signal between the base and emitter, but current cannot flow in that circuit during the part of the cycle that reverse-biases the base-emitter diode junction. Therefore, the transistor will remain in cutoff mode throughout that portion of the cycle. It will “turn on” in its active mode only when the input voltage is of the correct polarity to forward-bias the base-emitter diode, and only when that voltage is sufficiently high to overcome the diode’s forward voltage drop. Remember that bipolar transistors are current-controlled devices : they regulate collector current based on the existence of a base-to-emitter current , not base-to-emitter voltage .

The only way we can get the transistor to reproduce the entire waveform as the current through the speaker is to keep the transistor in its active mode the entire time. This means we must maintain current through the base during the entire input waveform cycle. Consequently, the base-emitter diode junction must be kept forward-biased at all times. Fortunately, this can be accomplished with a DC bias voltage added to the input signal. By connecting a sufficient DC voltage in series with the AC signal source, forward-bias can be maintained at all points throughout the wave cycle. (Figure below)

Vbias keeps transistor in the active region.

Undistorted output current I(v(1) due to Vbias

With the bias voltage source of 2.3 volts in place, the transistor remains in its active mode throughout the entire cycle of the wave, faithfully reproducing the waveform at the speaker. Notice that the input voltage (measured between nodes 1 and 0) fluctuates between about 0.8 volts and 3.8 volts, a peak-to-peak voltage of 3 volts just as expected (source voltage = 1.5 volts peak). The output (speaker) current varies between zero and almost 300 mA, 180° out of phase with the input (microphone) signal.

The illustration in the figure below is another view of the same circuit, this time with a few oscilloscopes (“scopemeters”) connected at crucial points to display all the pertinent signals.

Input is biased upward at base. Output is inverted.

The need for biasing a transistor amplifier circuit to obtain full-waveform reproduction is an important consideration . A separate section of this chapter will be devoted entirely to the subject of biasing and biasing techniques. For now, it is enough to understand that biasing may be necessary for proper voltage and current output from the amplifier.

Now that we have a functioning amplifier circuit, we can investigate its voltage, current, and power gains. The generic transistor used in these SPICE analyses has a β of 100, as indicated by the short transistor statistics printout included in the text output in Table below (these statistics were cut from the last two analyses for brevity’s sake).

BJT SPICE model parameters.

β is listed under the abbreviation “bf,” which actually stands for “beta, forward” . If we wanted to insert our own β ratio for analysis, we could have done so on the .model line of the SPICE netlist.

Since β is the ratio of collector current to base current, and we have our load connected in series with the collector terminal of the transistor and our source connected in series with the base, the ratio of output current to input current is equal to beta. Thus, our current gain for this example amplifier is 100, or 40 dB.

Voltage Gain

Voltage gain is a little more complicated to figure than current gain for this circuit. As always, voltage gain is defined as the ratio of output voltage divided by the input voltage. In order to experimentally determine this, we modify our last SPICE analysis to plot output voltage rather than output current so we have two voltage plots to compare in the figure below.

V(3), the output voltage across r spkr , compared to the input.

Plotted on the same scale (from 0 to 4 volts), we see that the output waveform in Figure above has a smaller peak-to-peak amplitude than the input waveform, in addition to being at a lower bias voltage, not elevated up from 0 volts like the input. Since voltage gain for an AC amplifier is defined by the ratio of AC amplitudes, we can ignore any DC bias separating the two waveforms. Even so, the input waveform is still larger than the output, which tells us that the voltage gain is less than 1 (a negative dB figure).

Low voltage gain is not characteristic of all common-emitter amplifiers. It is a consequence of the great disparity between the input and load resistances. Input resistance (R1) here is 1000 Ω, while the load (speaker) is only 8 Ω. Because the current gain of this amplifier is determined solely by the β of the transistor, and because that β figure is fixed, the current gain for this amplifier won’t change with variations in either of these resistances. However, voltage gain is dependent on these resistances. If we alter the load resistance, making it a larger value, it will drop a proportionately greater voltage for its range of load currents, resulting in a larger output waveform. Try another simulation, only this time with a 30 Ω in the figure below load instead of an 8 Ω load.

Increasing r spkr to 30 Ω increases the output voltag

This time the output voltage waveform in the figure above is significantly greater in amplitude than the input waveform. Looking closely, we can see that the output waveform crests between 0 and about 9 volts: approximately 3 times the amplitude of the input voltage.

We can do another computer analysis of this circuit, this time instructing SPICE to analyze it from an AC point of view, giving us peak voltage figures for input and output instead of a time-based plot of the waveforms. (Table below)

SPICE netlist for printing AC input and output voltages.

Peak voltage measurements of input and output show an input of 1.5 volts and an output of 4.418 volts. This gives us a voltage gain ratio of 2.9453 (4.418 V / 1.5 V), or 9.3827 dB.

Solving for the voltage gain:

Because the current gain of the common-emitter amplifier is fixed by β, and since the input and output voltages will be equal to the input and output currents multiplied by their respective resistors, we can derive an equation for approximate voltage gain:

As you can see, the predicted results for voltage gain are quite close to the simulated results. With perfectly linear transistor behavior, the two sets of figures would exactly match. SPICE does a reasonable job of accounting for the many “quirks” of bipolar transistor function in its analysis, hence the slight mismatch in voltage gain based on SPICE’s output.

These voltage gains remain the same regardless of where we measure output voltage in the circuit: across collector and emitter, or the series load resistor as we did in the last analysis. The amount of output voltage change for any given amount of input voltage will remain the same. Consider the two following SPICE analyses as proof of this. The first simulation in the figure below is time-based, to provide a plot of input and output voltages. You will notice that the two signals are 180o out of phase with each other. The second simulation in Table below is an AC analysis, to provide simple, peak voltage readings for input and output.

Common-emitter amplifier shows a voltage gain with R spkr =30Ω SPICE netlist for AC analysis

We still have a peak output voltage of 4.418 volts with a peak input voltage of 1.5 volts.

So far, the example circuits shown in this section have all used NPN transistors. PNP transistors are just as valid to use as NPN in any amplifier configuration, as long as the proper polarity and current directions are maintained, and the common-emitter amplifier is no exception. The output inversion and gain of a PNP transistor amplifier are the same as its NPN counterpart, just the battery polarities are different.

PNP version of common emitter amplifier.

• Common-emitter transistor amplifiers are so-called because the input and output voltage points share the emitter lead of the transistor in common with each other, not considering any power supplies.
• Transistors are essentially DC devices: they cannot directly handle voltages or currents that reverse direction. To make them work for amplifying AC signals, the input signal must be offset with a DC voltage to keep the transistor in its active mode throughout the entire cycle of the wave. This is called biasing .
• If the output voltage is measured between emitter and collector on a common-emitter amplifier, it will be 180° out of phase with the input voltage waveform. Thus, the common-emitter amplifier is called an inverting amplifier circuit.
• The current gain of a common-emitter transistor amplifier with the load connected in series with the collector is equal to β. The voltage gain of a common-emitter transistor amplifier is approximately given here:

• Where “Rout” is the resistor connected in series with the collector and “Rin” is the resistor connected in series with the base.

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• Class A BJT Amplifiers Worksheet
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Common Emitter configuration, Input and Output Characteristics

 common emitter configuration:.

Two terminals are needed for input and two terminals for output. Transistors have three terminals, so one terminal have to be taken as common terminal for both input and output. In Common Emitter configuration, emitter terminal is taken as common for both input and output. So input is given between base and the emitter terminals and output is taken between collector and emitter terminals. This is the most commonly used configuration.

Circuit diagram of Common Emitter NPN and PNP Transistor:

Input voltage V BE is applied between base and emitter terminals and output voltage V CE is applied across emitter and collector. The output current I C is taken across the emitter and collector terminals. The input side is forward biased and the output side is reverse biased.

Emitter base region acts like forward biased diode and so the depletion region is very small.  Emitter collector region acts like reverse biased diode and the depletion region is large. The input current I B is measured in µA because the base region is very lightly doped. 

  The input and output impedance are moderate in common emitter configuration and thus the current and voltage gain is moderate and the power gain is high. So this configuration is widely used for amplification. 

Input Characteristics of Common Emitter Configuration:

  Input characteristics are the relationship between the input current and the input voltage keeping output voltage constant. Here the input current is the base current I B , input voltage is base emitter voltage V BE and the output voltage is collector emitter voltage V CE .

First the output voltage V CE is kept at zero and the input voltage V BE is gradually increased and the input current IB is noted. Then again the output voltage V CE is increased like 10V, 20V and kept constant and by increasing the input voltage V BE , the input current I B is noted.

From the results it is observed that when the input voltage V BE is increased initially there is no current produced, further when it is increased the input current I B increases steeply. When the output voltage V CE is further increased the curve shifts right side.

Output Characteristics of Common Emitter Configuration:

  Output characteristics is the relationship between the output current and the output voltage keeping input current constant. Here the values of output current I C and the output voltage V CE is noted keeping input current I B constant.

In active region when the output voltage is increased there is very slight change in the output voltage. The curve looks almost flat in the active region. Cut off region is the region where the input current is below zero. When both the junctions are forward biased, it is in saturation region.

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Common Emitter Configuration & its characteristics

Common Emitter Configuration:

           The most frequently encountered transistor configuration appears in Fig. for the  PNP and NPN transistors. It is called the common emitter configuration since the emitter is common or reference to both the input and output terminals (in this case common to both the base and collector terminals). Two sets of characteristics are again  necessary to describe fully the behaviour of the common emitter configuration one for  the input or base-emitter circuit and one for the output or  collector-emitter circuit. Both are shown in the figure.

                     The emitter, collector, and base currents are shown in their actual conventional  current direction.Even though the transistor configuration has changed, the current  relations developed earlier for the common base configuration are still applicable. That is,             

                                     I E = I C + I B    and  I C = α  I E

                    For the common emitter configuration the output characteristics are a plot of the  output current (I C ) versus output voltage (V CE ) for a range of values of input current  (I B ).The input characteristics are a plot of the input current (I B ) versus the input voltage (V BE ) for a range of values of output voltage (V CE ).

Common Emitter Configuration Characteristics:

        Note that on the characteristics of common emitter configuration the magnitude of I B is in microamperes, compared to milliamperes of I C . Consider also that the curves of I B are not as  horizontal as those obtained for I E in the common-base configuration, indicating that  the collector-to-emitter voltage will influence the magnitude of the collector current.

             The active region for the common emitter configuration is that portion of the   upper-right quadrant that has the greatest linearity, that is, that region in which the  curves for I B  are nearly straight and equally spaced. In Fig. shown this region exists  to the right of the vertical dashed line at V CE(sat)   and above the curve for I B equal to  zero.The region to the left of V CE(sat)   is called the saturation region.

              In the active region of a common emitter amplifier the collector-base junction  is reverse-biased, while the base-emitter junction is forward-biased.

             You will recall that these were the same conditions that existed in the active region of the common base configuration .The active region of the common emitter  configuration can be employed for voltage, current, or power amplification. The cutoff region for the common emitter configuration is not as well defined as  for the common base configuration . 

              Note on the collector characteristics of the figure  that I C is not equal to zero when I B is zero. For the common base configuration , when  the input current I E was equal to zero, the collector current was equal only to the reverse saturation current I CO , so that the curve I E = 0 and the voltage axis were, for  all practical purposes, one.

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Input and Output Characteristics of Common Emitter Configuration.

Since transistor is a three terminal device, therefore, it can be connected in a circuit in three different ways:

• Common-base configuration
• Common-emitter configuration
• Common-collector configuration

Definition – In this configuration, emitter terminal of transistor is common between the input and output circuits.

The graphs showing the relationship between different currents and voltages of a transistor are known as the characteristics of the transistor . The characteristics of a transistor are of two types:

• Input Characteristics.
• Output Characteristics.
• 1.1 Input Characteristics common emitter configuration
• 1.2.1 Active Region
• 1.2.2 Cutoff Region
• 1.2.3 Saturation region
• 1.3 What are the input and output characteristics of a transistor?
• 1.4 What is input characteristics of common emitter configuration?
• 1.5 What are the input and output characteristics of common emitter configuration?

input and output characteristics of common emitter configuration

The graph between the variation of voltage and variation of currents when emitter of a transistor is common to both input and output circuits are known as common emitter characteristics of a transistor.

Circuit diagram to study input and output characteristics of common emitter configuration of a transistor is shown in the figure below.

Characteristics of a transistor in common emitter configuration are of two types:

•  input characteristics common emitter configuration.
•  output characteristics common emitter configuration.

Input Characteristics common emitter configuration

The graphs showing the variation of base current ‎I B (input) with the variation of emitter-base voltage ( ‎V EB ) at a constant collector-emitter voltage ( V CE ) are called input characteristics. 

The set of input characteristics are shown in the figure.

The input characteristics of a PNP transistor are just like the characteristics of a forward-biased diode when the collector of the transistor is short-circuited to the emitter and the emitter is forward biased. 

When ‎V BE = 0, ‎I B = 0 because in this case both the junction i.e. emitter-base junction and collector-base junction are short-circuited. As the value of ‎V CE increases, then due to the Early effect, the width of the base region decreases, and hence the recombination of holes and electrons in the base agent decreases. As a result of this, the recombination current ( i.e. base current ‎I B ) decreases at a given Value of ‎V BE .

Output characteristics common emitter configuration 

The graphs showing the variation of collector current ‎I C (output) with the variation of collector-emitter voltage at constant base current ‎I B (input) are known as output characteristics of a transistor in the common-emitter configuration.

A set of output characteristics are shown in the figure.

output characteristics of a transistor in common emitter configuration are divided into three regions:

Active Region

In this region, collector junction is Reverse Biased and emitter junction is forward biased. This region lies above ‎ I B = 0 and to the right of the ordinate ‎V CE = a few tenths of a volt. For a given value of ‎I B the value of ‎I C increases due to early effect as ( ‎V CE ) increases.

Note. Transistor is operated in an active region if it is used as an amplifier. 

Cutoff Region

The cutoff region lies below ‎I B = 0. However, it is clear from the figure that the collector current has a significant value under this condition. In order to cut off the transistor, the emitter junction has to be made slightly reverse biased in addition to I B .=0 ‎.

Saturation region

In this region, both emitter and collector junctions are forward biased equal to cut in voltage. Saturation region lies close to the zero voltage axis where all the curves coincide and fall rapidly toward the origin.

What are the input and output characteristics of a transistor?

The graphs showing the relationship between different currents and voltages of a transistor are known as the characteristics of the transistor.

What is input characteristics of common emitter configuration?

The graphs showing the variation of base current ‎I B (input) with the variation of emitter-base voltage ( ‎V EB ) at a constant collector-emitter voltage ( V CE ) are called input characteristics.

What are the input and output characteristics of common emitter configuration?

Common Emitter Amplifier

• Boris Poupet
• bpoupet@hotmail.fr
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Presenting the Common Emitter Amplifier

In the next three tutorials, including this one, we will present the three elementary topologies of bipolar transistors based amplifiers : the Common Emitter Amplifier , the Common Collector Amplifier and finally, the Common Base Amplifier .

We begin this series of tutorial by dealing with the most common type of amplifier found in an endless list of applications : the Common Emitter Amplifier that we will refer in the following as “CEA”.

The first figure below presents the simplified electrical circuitry of a CEA configuration. The aim of Figure 1 is to purely show the general configuration of a CEA. However, some important elements of a real CEA architecture are missing and will be presented more in detail in the next section.

In this configuration, the input signal is delivered to the base branch, whereas the output is taken to the collector branch of the bipolar transistor. The name “Common Emitter” comes from the fact that the emitter branch is directly wired to the ground of the circuit.

Full CEA configuration

The simplified diagram given in Figure 1 does not include any biasing circuit, coupling and decoupling capacitors etc. A real circuit of a CEA configuration is given in Figure 2 :

First of all let’s deal with the added resistors:

• A resistance R L is in parallel with the resistance R C of the collector, it represents a load, that is to say the next stage of the circuit after the CEA : it can be an antenna, a speaker or simply another amplifier or stage of the electronic circuit.
• The resistance R S represents the internal resistance of the sine source.
• The resistor R 1 and R 2 are in parallel with the base branch of the bipolar transistor and form what is commonly known as a voltage network divider . This voltage divider as shown in the tutorial “ Biasing a Bipolar Transistor in Common Emitter Configuration ” is the most suitable biasing method since it improves the stability of the amplifier.

Moreover, three capacitosr have been added :

• The capacitor C 1 and C 3 are commonly known as “coupling capacitors”. The coupling capacitance C 1 lets only the alternative current (AC) signal pass as an input of the CEA configuration while blocking the direct current (DC) to go from the supply to the source. The coupling capacitance C 3 does the same by blocking any DC component coming from or going to the load R L . To summarize, C 1 and C 3 allow the AC signal to cross completely the CEA but blocks the DC signals to enter in the CEA.
• The emitter branch is wired to the ground through a “decoupling” or “derivation” capacitance C 2 . It is shown later in the tutorial the importance of this capacitance to amplify the voltage signal.

With this configuration, the DC is restricted to bias the CEA and it sinks to the ground while the AC can cross the CEA from the input to the output. Since this circuit works with DC and AC signals, both need to be taken into consideration when analyzing the CEA configuration as it is done in the next two sections.

Equivalent circuit in DC

In DC, the coupling and decoupling capacitor act as an open circuit. Considering this fact, the equivalent circuit in DC of Figure 2 is presented in Figure 3 below :

In this circuit, the base voltage V B is given by the network divider formula :

The base resistance R B is usually not considered in the calculation of V B since it is in a parallel configuration with the bias resistances and its value is most of the time at least superior of one order of magnitude than R 2 . However, for some configurations, this affirmation may not be valid or if one needs a high precision of the value of V B , the full formula should include the base resistance R B :

We can therefore express V E =V B -V BE where V BE =0.7 V is the threshold voltage of a silicon-based bipolar transistor.

Let’s suppose that the bipolar transistor current gain β is given by I C =β×I B with the collector current I C and base current I B , such as described in Figure 2 . We have already mentioned just before that R B >>R 2 , moreover, since I E ≅I C we can write from Figure 3 that R B ×I B =R E ×I C . When replacing I C by β×I B , the base current I B simplifies itself and we get the expression of the base resistance :

Equivalent circuit in AC

In AC, the coupling and decoupling capacitors are equivalent to a short circuit. Therefore, the emitter branch is shorted to the ground and the bias and collector are not included. Moreover, we introduce in the circuit a small diode emitter resistance r e =25 mV/I out that represents the dynamic resistance for small AC signals of the p/n junction of the bipolar transistor. When taking this into consideration, the equivalent circuit in AC of Figure 2 is given by Figure 4 below :

Input resistance

The total input resistance R in of a CEA configuration is given by the parallel configuration of the bias and base resistances R 1 //R 2 //R B :

Output resistance

The total output resistance R out of a CEA configuration is given by the parallel configuration of the collector and load resistances R C //R L :

Voltage gain

The voltage gain of a CEA configuration is simply defined by A V =V out /V in . When considering the circuit presented in Figure 4 , we have V out =R out ×I out and V in =r e ×I out . The output current simplifies itself and the voltage gain is given by the ratio :

Equation 5 gives the expression of the voltage gain when the derivation capacitance behaves like a perfect short circuit, that is to say at high working frequencies.

Importance of the derivation capacitance

It is interesting to see the effect of the derivation capacitance C 2 presented in Figure 2 . Indeed, if this capacitance is not used, the emitter branch is not shorted to the ground in Figure 4 and the total resistance in this branch is R E +r e instead of r e . Therefore, the voltage gain becomes :

Usually the emitter resistance satisfies R E >>r e so that we can approximate the voltage gain by A V =R out /R E . Since the emitter resistance is much greater than the small diode resistance, the voltage gain is very much decreased.

As an example, typical values are : R C //R L =1 kΩ, R E =500 Ω and r e =5 Ω.

• With no derivation capacitance, the voltage gain is A V =1000/505= 1.98
• With a derivation capacitance, the voltage gain becomes A V =1000/5= 200

The derivation capacitance in the emitter branch is therefore very important to amplify the voltage signal. Equation 6 gives the expression of the voltage gain when the derivation capacitance behaves as a perfect open circuit, that is to say at very low working frequencies or in DC mode.

Attenuation by the source

In Figure 4 we have not considered the source with its internal resistance R S presented in Figure 2 . In reality, the voltage gain is affected by a factor V B /V S that represents the dimming produced by the small internal resistance of the source. The attenuated voltage gain is A V ‘=A V ×(V B /V S ) and this factor is given by :

This factor is usually very close to 1 so often not considered to get an approximate value of the gain of a CEA configuration.

Current gain

The current gain is defined by A I =I out /I in where I in =V in /R in and I out =V out /R out . It comes then :

The voltage gain A V can be developed with the expression of Equation 5 which simplifies R out and leaves :

Since R in >>r e , the current gain of a CEA configuration is high.

Phase inversion

One very important characteristic of the CEA that we have yet not mentioned is that it inverts the phase of the output signals. Let’s consider for example a CEA with a voltage gain of 10 that has an input voltage of 2 V peak to peak and visualize both input and output voltages on the same figure :

The phase inversion basically means that the maximum of the output voltage matches the minimum of the input voltage and the minimum of the output signal matches the maximum of the input signal.

In conclusion, we have seen how does a Common Emitter Amplifier (CEA) configuration behave. At first, a simplified circuit is presented to get introduced to the main aspects of this amplifier. We have seen afterwards the architecture of the full circuit of a CEA by understanding the role of bias and load resistor and coupling and decoupling capacitors. From analyzing the equivalent circuit in DC and AC modes, we have given the expressions of important parameters : the input and output impedance and the voltage and current gains. The CEA present high voltage and current gains that are enhanced by the presence of a derivation capacitance in the emitter branch, it also presents high input and output impedance, making it suitable as a universal amplifier for many applications. One other characteristic, specific only to CEAs is the phase inversion of 180 °=π rad between the input and output signals.

In the next tutorial we will analyze another type of amplifier that delivers the output from its emitter branch : the Common Collector Amplifier.

More tutorials in Amplifiers

• Phase Splitter

Class D Amplifiers

• Frequency Response of Amplifiers

Input and Output Impedances of Amplifiers

• Class C Amplifiers
• Class AB Amplifiers
• Class B Amplifiers
• Class A amplifiers
• Amplifier Classes
• MOSFET Amplifier

RELATED ARTICLES

Introduction to Electronic Amplifiers

Common Emitter Amplifier Circuit Working & Its Characteristics

There are different types of transistor amplifiers operated by using an AC signal input. This is interchanged between the positive value and negative value, hence this is the one way of presenting the common emitter amplifier circuit to function between two peak values. This process is known as the biasing amplifier and it is an important amplifier design to establish the exact operating point of a transistor amplifier which is ready to receive the signals hence it can reduce any distortion to the output signal. In this article, we will discuss common emitter amplifier analysis.

What is an Amplifier?

The Amplifier is an electronic circuit that is used to increase the strength of a weak input signal in terms of voltage, current, or power. The process of increasing the strength of a weak signal is known as Amplification. One most important constraint during the amplification is that only the magnitude of the signal should increase and there should be no changes in the original signal shape. The transistor (BJT, FET) is a major component in an amplifier system. When a transistor is used as an amplifier, the first step is to choose an appropriate configuration, in which the device is to be used. Then, the transistor should be biased to get the desired Q-point. The signal is applied to the amplifier input and output gain is achieved.

What is a Common Emitter Amplifier?

The common emitter amplifier is a three basic single-stage bipolar junction transistor and is used as a voltage amplifier. The input of this amplifier is taken from the base terminal, the output is collected from the collector terminal and the emitter terminal is common for both the terminals. The basic symbol of the common emitter amplifier is shown below.

Common Emitter Amplifier Configuration

In electronic circuit design, there are three kinds of transistor configurations are used like common emitter, common base, and common collector, In that, the most frequently used one is common emitter due to its main attributes.

This kind of amplifier includes the signal which is given to the base terminal then the output is received from the collector terminal of the circuit. But, as the name suggests, the main attribute of the emitter circuit is familiar for both the input as well as output.

The configuration of a common emitter transistor is widely used in most electronic circuit designs. This configuration is evenly appropriate to both the transistors like PNP and NPN transistors but NPN transistors are most frequently used due to the widespread use of these transistors.

In Common Emitter Amplifier Configuration, the Emitter of a BJT is common to both the input and output signal as shown below. The arrangement is the same for a PNP transistor , but bias will be opposite w.r.t NPN transistor.

Operation of Common Emitter Amplifier

When a signal is applied across the emitter-base junction, the forward bias across this junction increases during the upper half cycle. This leads to an increase in the flow of electrons from the emitter to a collector through the base, hence increases the collector current. The increasing collector current makes more voltage drops across the collector load resistor RC.

The negative half cycle decreases the forward bias voltage across the emitter-base junction. The decreasing collector-base voltage decreases the collector current in the whole collector resistor Rc. Thus, the amplified load resistor appears across the collector resistor. The common emitter amplifier circuit is shown above.

From the voltage waveforms for the CE circuit shown in Fig. (b), It is seen that there is a 180-degree phase shift between the input and output waveforms.

Working of Common Emitter Amplifier

The below circuit diagram shows the working of the common emitter amplifier circuit and it consists of voltage divider biasing, used to supply the base bias voltage as per the necessity. The voltage divider biasing has a potential divider with two resistors are connected in a way that the midpoint is used for supplying base bias voltage.

There are different types of electronic components in the common emitter amplifier which are R1 resistor is used for the forward bias, the R2 resistor is used for the development of bias, the RL resistor is used at the output it is called the load resistance. The RE resistor is used for thermal stability. The C1 capacitor is used to separate the AC signals from the DC biasing voltage and the capacitor is known as the coupling capacitor .

The figure shows that the bias vs gain common emitter amplifier transistor characteristics if the R2 resistor increases then there is an increase in the forward bias and R1 & bias are inversely proportional to each other. The alternating current is applied to the base of the transistor of the common emitter amplifier circuit then there is a flow of small base current. Hence there is a large amount of current flow through the collector with the help of the RC resistance. The voltage near the resistance RC will change because the value is very high and the values are from 4 to 10kohm. Hence there is a huge amount of current present in the collector circuit which amplified from the weak signal, therefore common emitter transistors work as an amplifier circuit.

Voltage Gain of Common Emitter Amplifier

The current gain of the common emitter amplifier is defined as the ratio of change in collector current to the change in base current. The voltage gain is defined as the product of the current gain and the ratio of the output resistance of the collector to the input resistance of the base circuits. The following equations show the mathematical expression of the voltage gain and the current gain.

β = ΔIc/ ΔIb

Av = β Rc/Rb

Circuit Elements and their Functions

The common emitter amplifier circuit elements and their functions are discussed below.

Biasing Circuit/ Voltage Divider

The resistances R1, R2, and RE used to form the voltage biasing and stabilization circuit . The biasing circuit needs to establish a proper operating Q-point otherwise, a part of the negative half cycle of the signal may be cut-off in the output.

Input Capacitor (C1)

The capacitor C1 is used to couple the signal to the base terminal of the BJT. If it is not there, the signal source resistance, Rs will come across R2, and hence, it will change the bias. C1 allows only the AC signal to flow but isolates the signal source from R2

Emitter Bypass Capacitor (CE)

An Emitter bypass capacitor CE is used parallel with RE to provide a low reactance path to the amplified AC signal. If it is not used, then the amplified AC signal following through RE will cause a voltage drop across it, thereby dropping the output voltage.

Coupling Capacitor (C2)

The coupling capacitor C2 couples one stage of amplification to the next stage. This technique used to isolate the DC bias settings of the two coupled circuits.

CE Amplifier Circuit Currents

Base current iB = IB +ib where,

IB = DC base current when no signal is applied.

ib = AC base when AC signal is applied and iB = total base current.

Collector current iC = IC+ic where,

iC = total collector current.

IC = zero signal collector current.

ic = AC collector current when the AC signal is applied.

Emitter Current iE = IE + ie where,

IE = Zero signal emitter current.

Ie = AC emitter current when AC signal is applied.

iE = total emitter current.

Common Emitter Amplifier analysis

The first step in AC analysis of Common Emitter amplifier circuit is to draw the AC equivalent circuit by reducing all DC sources to zero and shorting all the capacitors. The below figure shows the AC equivalent circuit.

The next step in the AC analysis is to draw an h-parameter circuit by replacing the transistor in the AC equivalent circuit with its h-parameter model. The below figure shows the h-parameter equivalent circuit for the CE circuit.

The typical CE circuit performance is summarised below:

• Device input impedance, Zb = hie
• Circuit input impedance, Zi = R1 || R2 || Zb
• Device output impedance, Zc= 1/hoe
• Circuit output impedance, Zo = RC || ZC ≈ RC
• Circuit voltage gain, Av = -hfe/hie*(Rc|| RL)
• Circuit current gain, AI = hfe. RC. Rb/ (Rc+RL) (Rc+hie)
• Circuit power gain, Ap = Av * Ai

CE Amplifier Frequency Response

The voltage gain of a CE amplifier varies with signal frequency. It is because the reactance of the capacitors in the circuit changes with signal frequency and hence affects the output voltage. The curve drawn between voltage gain and the signal frequency of an amplifier is known as frequency response. The below figure shows the frequency response of a typical CE amplifier.

From the above graph, we observe that the voltage gain drops off at low (< FL) and high (> FH) frequencies, whereas it is constant over the mid-frequency range (FL to FH).

At Low Frequencies (< FL) The reactance of coupling capacitor C2 is relatively high and hence very small part of the signal will pass from the amplifier stage to the load.

Moreover, CE cannot shunt the RE effectively because of its large reactance at low frequencies. These two factors cause a drops off of voltage gain at low frequencies.

At High Frequencies (> FH) The reactance of coupling capacitor C2 is very small and it behaves as a short circuit. This increases the loading effect of the amplifier stage and serves to reduce the voltage gain.

Moreover, at high frequencies, the capacitive reactance of base-emitters junction is low which increases the base current. This frequency reduces the current amplification factor β. Due to these two reasons, the voltage gain drops off at a high frequency.

At Mid Frequencies (FL to FH) The voltage gain of the amplifier is constant. The effect of the coupling capacitor C2 in this frequency range is such as to maintain a constant voltage gain. Thus, as the frequency increases in this range, the reactance of CC decreases, which tends to increase the gain.

However, at the same time, lower reactance means higher almost cancel each other, resulting in a uniform fair at mid-frequency.

We can observe the frequency response of any amplifier circuit is the difference in its performance through changes within the input signal’s frequency because it shows the frequency bands where the output remains fairly stable. The circuit bandwidth can be defined as the frequency range either small or big among ƒH & ƒL.

So from this, we can decide the voltage gain for any sinusoidal input in a given range of frequency. The frequency response of a logarithmic presentation is the Bode diagram. Most of the audio amplifiers have a flat frequency response that ranges from 20 Hz – 20 kHz. For an audio amplifier, the frequency range is known as Bandwidth.

Frequency points like ƒL & ƒH are related to the lower corner & the upper corner of the amplifier which are the gain falls of the circuits at high as well as low frequencies. These frequency points are also known as decibel points. So the BW can be defined as

BW = fH – fL

The dB (decibel) is 1/10th of a B (bel), is a familiar non-linear unit to measure gain & is defined like 20log10(A). Here ‘A’ is the decimal gain which is plotted over the y-axis.

The maximum output can be obtained through the zero decibels which communicate toward a magnitude function of unity otherwise it occurs once Vout = Vin when there is no reduction at this frequency level, so

VOUT/VIN = 1, so 20log(1) = 0dB

We can notice from the above graph, the output at the two cut-off frequency points will decrease from 0dB to -3dB & continues to drop at a fixed rate. This reduction within gain is known commonly as the roll-off section of the frequency response curve. In all basic filter and amplifier circuits, this roll-off rate can be defined as 20dB/decade, which is equal to a 6dB/octave rate. So, the order of the circuit is multiplied with these values.

These -3dB cut-off frequency points will describe the frequency where the o/p gain can be decreased to 70 % of its utmost value. After that, we can properly say that the frequency point is also the frequency at which the gain of the system has reduced to 0.7 of its utmost value.

Common Emitter Transistor Amplifier

The circuit diagram of the common emitter transistor amplifier has a common configuration and it is a standard format of transistor circuit whereas voltage gain is desired. The common emitter amplifier is also converted as an inverting amplifier. The different types of configurations in transistor amplifiers are common base and the common collector transistor and the figure are shown in the following circuits.

Characteristics of Common Emitter Amplifier

• The voltage gain of a common emitter amplifier is medium
• The power gain is high in the common emitter amplifier
• There is a phase relationship of 180 degrees in input and output
• In the common emitter amplifier, the input and output resistors are medium.

The characteristics graph between the bias and the gain is shown below.

Transistor Bias Voltage

The Vcc (supply voltage) will determine the utmost Ic (collector current) once the transistor is activated. The Ib (base current) for the transistor can be found from the Ic (collector current) & the DC current gain β (Beta) of the transistor.

VB = VCC R2/R1+R2

Sometimes, ‘β’ is referred to as ‘hFE’ which is the forward current gain of the transistor within the CE configuration. Beta (β) is a fixed ratio of the two currents like Ic and Ib, so it doesn’t contain units. So a small change within the base current will make a huge change within the collector current.

The same type of transistors as well as their part number will contain huge changes within their ‘β’ values. For instance, the NPN transistor like BC107 includes a Beta value (DC current gain in between 110 – 450 based on the datasheet. So one transistor may include a 110 Beta value whereas another may include of 450 Beta value, however, both the transistors are NPN BC107 transistors because Beta is a feature of the structure of the transistor but not of its function.

When the base or emitter junction of the transistor is connected forward bias, then the emitter voltage ‘Ve’ will be a single junction where voltage drop is dissimilar to the voltage of the Base terminal. The emitter current (Ie) is nothing but the voltage across the emitter resistor. This can be calculated simply through Ohm’s Law. The ‘Ic’ (collector current) can be approximated, as it is approximately a similar value to the emitter current.

Input and Output Impedance of Common Emitter Amplifier

In any electronic circuit design, impedance levels are one of the main attributes that need to consider. The value of input impedance is normally in the region of 1kΩ, while this can differ significantly based on the conditions as well as values of the circuit. The less input impedance will result from the truth that the input is given across the two terminals of the transistor-like base & emitter because there is a forward-biased junction.

Also, the o/p impedance is comparatively high because it varies significantly again on the values of selected electronic component values & allowed current levels. The o/p impedance is a minimum of 10kΩ otherwise possibly high. But if the current drain permits high levels of current to be drawn, then the o/p impedance will be decreased significantly. The impedance or resistance level comes from the truth that the output is used from the collector terminal because there is a reverse-biased junction.

Single Stage Common Emitter Amplifier

The single-stage common emitter amplifier is shown below and different circuit elements with their functions are described below.

Biasing Circuit

The circuits like biasing as well as stabilization can be formed with resistances like R1, R2 & RE

Input Capacitance (Cin)

The input capacitance can be denoted with ‘Cin’ which is used to combine the signal toward the base terminal of the transistor.

If this capacitance is not used, then the resistance of the signal source will approach across the resistor ‘R2’ to alter the bias. This capacitor will allow simply AC signal to supply.

The connection of the emitter bypass capacitor can be done in parallel to RE to give a low reactance lane toward the amplified AC signal. If it is not utilized, then the amplified AC signal will flow throughout RE to cause a voltage drop across it, so the o/p voltage can be shifted.

Coupling Capacitor (C)

This coupling capacitor is mainly used to combine the amplified signal toward the o/p device so that it will allow simply AC signal to supply.

Once a weak input AC signal is given toward the base terminal of the transistor, then a small amount of base current will supply, because of this transistor act, high AC. current will flow throughout collector load (RC), so high voltage can come into view across the collector load as well as the output. Thus, a feeble signal is applied toward the base terminal which appears in the amplified form within the collector circuit. The amplifier’s voltage gain like Av is the relation between the amplified input and output voltages.

Frequency Response & Bandwidth

The amplifier’s voltage gain like Av for several input frequencies can be concluded. Its characteristics can be drawn on both the axis like a frequency on X-axis whereas voltage gain is on Y-axis. The graph of frequency response can be attained which is shown in the characteristics. So we can observe that the gain of this amplifier can be decreased at very high and low frequencies, however, it stays stable over an extensive range of mid-frequency area.

The fL or low cut off frequency can be defined as when the frequency is below 1. The range of frequency can be decided at which the amplifier gain is double the gain of mid-frequency.

The fL(upper cut off frequency) can be defined as when the frequency is in the high range at which the amplifier’s gain is 1/√2 times the gain of mid-frequency.

Bandwidth can be defined as the interval of frequency among low-cut off & upper cut-off frequencies.

BW = fU – fL

Common Emitter Amplifier Experiment Theory

The main intention of this CE NPN transistor amplifier is to investigate its operation.

The CE amplifier is one of the main configurations of a transistor amplifier. In this test, the learner will design as well as examine a fundamental NPN CE transistor amplifier. Suppose, the learner has some knowledge on the theory of transistor amplifier like the use of AC equivalent circuits. So the learner is estimated to design his/her own process to perform the experiment in the lab, once the pre-lab analysis is completely done, then he can analyze & summarize the experiment results in the report.

The required components are NPN transistors – 2N3904 & 2N2222), VBE = 0.7V, Beta = 100, r’e = 25mv/IE in the analysis of Pre-lab.

As per the circuit diagram, calculate the DC parameters like Ve, IE, VC, VB & VCE with approximate technique. Sketch the ac equivalent circuit & calculate the Av (voltage gain ), Zi (input impedance) & Zo (output impedance). Also sketch the composite waveforms predictable at different points like A, B, C, D & E within the circuit. At point ‘A’, assumer Vin like 100 mv peak, Sine wave with 5 kHz.

For a voltage amplifier, draw the circuit with input impedance, a voltage source which is dependant as well as o/p impedance

Measure the input impedance value like Zi through inserting a test resistor within a series through the input signals toward the amplifier & measure how much the signal of the ac generator will appear really at the amplifier’s input.

To determine output impedance, take out the load resistor momentarily & calculate the unloaded ac o/p voltage. After that, put back the load resistor, again measure the ac o/p voltage. To determine the output impedance, these measurements can be used.

Experiment in Lab

Design the circuit accordingly and check all the above calculations. Utilize DC coupling as well as dual-trace on the oscilloscope. After that takeout common-emitter momentarily & again measure the o/p voltage. Evaluate the outcomes using your Pre-lab computations.

The advantages of a common emitter amplifier include the following.

• The common emitter amplifier has a low input impedance and it is an inverting amplifier
• The output impedance of this amplifier is high
• This amplifier has the highest power gain when combined with medium voltage and current gain
• The current gain of the common emitter amplifier is high

Disadvantages

The disadvantages of a common emitter amplifier include the following.

• In the high frequencies, the common emitter amplifier does not respond
• The voltage gain of this amplifier is unstable
• The output resistance is very high in these amplifiers
• In these amplifiers, there is a high thermal instability
• High output resistance

Applications

The applications of a common emitter amplifier include the following.

• The common emitter amplifiers are used in the low-frequency voltage amplifiers.
• These amplifiers are used typically in the RF circuits.
• In general, the amplifiers are used in the Low noise amplifiers
• The common emitter circuit is popular because it’s well-suited for voltage amplification, especially at low frequencies.
• Common-emitter amplifiers are also used in radio frequency transceiver circuits.
• Common emitter configuration commonly used in low-noise amplifiers.

This article discusses the working of the common emitter amplifier circuit. By reading the above information you have got an idea about this concept. Furthermore, any queries regarding this or if you want to implement electrical projects , please feel free to comment in the below section. Here is the question for you, what is the function of the common emitter amplifier?

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Hot-carrier transistors are a class of devices that leverage the excess kinetic energy of carriers. Unlike regular transistors, which rely on steady-state carrier transport, hot-carrier transistors modulate carriers to high-energy states, resulting in enhanced device speed and functionality. These characteristics are essential for applications that demand rapid switching and high-frequency operations, such as advanced telecommunications and cutting-edge computing technologies 1 , 2 , 3 , 4 , 5 . However, the traditional mechanisms of hot-carrier generation are either carrier injection 6 , 7 , 8 , 9 , 10 , 11 or acceleration 12 , 13 , which limit device performance in terms of power consumption and negative differential resistance 14 , 15 , 16 , 17 . Mixed-dimensional devices, which combine bulk and low-dimensional materials, can offer different mechanisms for hot-carrier generation by leveraging the diverse potential barriers formed by energy-band combinations 18 , 19 , 20 , 21 . Here we report a hot-emitter transistor based on double mixed-dimensional graphene/germanium Schottky junctions that uses stimulated emission of heated carriers to achieve a subthreshold swing lower than 1 millivolt per decade beyond the Boltzmann limit and a negative differential resistance with a peak-to-valley current ratio greater than 100 at room temperature. Multi-valued logic with a high inverter gain and reconfigurable logic states are further demonstrated. This work reports a multifunctional hot-emitter transistor with significant potential for low-power and negative-differential-resistance applications, marking a promising advancement for the post-Moore era.

Transistors can be divided into three groups according to Ng and Sze 1 , 2 , 3 : field-effect transistors, potential-effect transistors and hot-carrier transistors. The first two groups are represented by the metal–oxide–semiconductor field-effect transistor (MOSFET) and the bipolar junction transistor (BJT), respectively, which have achieved great success in modern integrated circuits, whereas the third group has advantages in speed and multifunction based on the excess kinetic energy of hot carriers 4 , 5 , mainly including the hot-electron transistor (HET) and the real-space-transfer transistor (RSTT). A HET uses a metal or a semiconductor as the base, and when electrons are injected into the base from the emitter, they become hot and fast because their energy is higher than those in the base, producing a short base transit time and a high-speed device 6 , 7 . Two-dimensional materials such as graphene and molybdenum disulfide (MoS 2 ) have been used as the base to further reduce the base transit time because of their low atomic thickness, providing a potential terahertz operation, which is promising in the next 6G technologies 8 , 9 , 10 , 11 . In contrast, an RSTT uses an electrical field to accelerate carriers, which, when they become hot enough, will transfer from one route to another, resulting in high-speed operation and a negative differential resistance (NDR) 12 , 13 , which is highly needed in various fields such as high-frequency oscillators 14 , 15 .

HETs and RSTTs provide potential high performance. However, the mechanisms of the hot-carrier generation are either carrier injection or acceleration, which may limit the device performance and function 7 , 8 , 9 , 13 . Neither of these devices can provide an ultralow subthreshold swing less than 60 mV dec −1 beyond the Boltzmann limit, which is highly needed for modern low-power applications 16 , 17 . In addition, for an RSTT, the NDR is limited when the device is fabricated using silicon (Si) and germanium (Ge) technology, which is compatible with mainstream semiconductor production. A novel mechanism of hot-carrier generation is needed to improve the power consumption and NDR of hot-carrier devices.

Mixed-dimensional electronic devices fabricated by combining bulk and low-dimensional materials can utilize the advantages of different dimensional materials in terms of geometric scale, and electrical and optical performance 18 , 19 , 20 , 21 , and may combine these advantages to provide a novel mechanism of hot-carrier generation. For low-dimensional materials such as graphene and carbon nanotubes, carrier mobility is high, which can be used to heat carriers using an electrical field. Meanwhile, various potential barriers can be formed using different energy-band combinations of bulk and low-dimensional materials, which can be used to emit high-energy carriers. Here we report a mixed-dimensional hot-emitter transistor (HOET) based on double graphene/germanium Schottky junctions. Using stimulated emission of heated carriers, the transistor achieves a subthreshold swing lower than 1 mV dec −1 and an NDR with a peak-to-valley current ratio greater than 100 at room temperature. Multi-valued logic applications with a high inverter gain and reconfigurable logic states are further demonstrated based on these characteristics.

Device structure and characteristics

The transistor is essentially composed of a monolayer graphene (Gr) with a gap cut in it and a p-type Ge substrate. Gr contacts Ge through the hafnium dioxide (HfO 2 ) window. The two separated Gr layers were used as the emitter (emitter-Gr) and the base (base-Gr), and the Ge substrate was used as the collector (Fig. 1a,b ). Devices were fabricated using Gr transfer and standard semiconductor processing. The high-quality monolayer Gr was grown by chemical vapour deposition and transferred onto the Ge substrate 22 (Extended Data Fig. 1 ). The gap in the Gr was fabricated using photolithography with a gap length from 2 μm to 75 μm (Fig. 1c and Methods ).

a , Illustration of the transistor structure, where monolayer Gr with a gap cut in it is on a p-Ge substrate (resistivity 1–10 Ω cm). The two separate Gr layers were used as the emitter (e) and base (b) contacting the Ge substrate through the HfO 2 window, and the Ge substrate as the collector (c), with the electrodes being Ti/Au. The channel length and width of the transistor are defined as those of the HfO 2 window. b , A diagram of the cross-section of the transistor showing monolayer Gr with a gap on a Ge substrate. c , Transistors with gap lengths of 2 μm to 75 μm were fabricated using photolithography and 9 of them are shown in the optical image. Scale bar, 100 μm. d , Transfer characteristics I c – V b show a negative abruptly changing collector current I c with an SS less than 1 mV dec −1 beyond the Boltzmann limit at room temperature. e , Output characteristics I c – V c show an NDR with a PVR of around 100.

The Gr is separated by the gap as tested by current–voltage ( I – V ) measurements (Extended Data Fig. 2 ). The I – V characteristics of the emitter-Gr/p-Ge junction and the base-Gr/p-Ge junction show an on-to-off current ratio of about 10 3 at ±3 V, indicating the existence of a Schottky barrier between Gr and Ge (Extended Data Fig. 3a ). The temperature-dependent I – V characteristics of the junction indicate a thermionic-emission-dominant mechanism where the Schottky barrier height was determined to be about 0.38 eV (Extended Data Fig. 3b and Methods ). See Extended Data Fig. 3 for more junction characteristics. For the transistor, the relationship of the collector current  I c  and the base voltage V b in the transfer characteristics ( I c – V b ) shows an abrupt current change beyond the Boltzmann limit where the subthreshold swing (SS) is below 1 mV dec −1 (Fig. 1d ), whereas the one of  I c  and the collector voltage V c in the output characteristics ( I c – V c ) shows an NDR with a peak-to-valley current ratio (PVR) around 100 (Fig. 1e ).

Ultralow subthreshold swing

The SS is a basic parameter to characterize the switching performance of a transistor. A smaller SS is preferred for low-power operation; however, it is usually larger than 60 mV dec −1 because of the Boltzmann limit 23 . When the HOET works, the emitter bias V e is grounded giving the transistor a common-emitter configuration. When the base bias V b increases, at a critical base bias V b-critical , a negative collector current I c is observed where the current change is rather abrupt (Figs. 1d and 2a ). At room temperature, the abrupt current change is beyond the Boltzmann limit where the minimum SS is in the range of 0.38–1.52 mV dec −1 as V c increases, and the range of the current with an SS less than 60 mV dec −1 is about 1 to 3 orders of magnitude, which could be further increased (Fig. 2b and Methods ). For a current with an SS less than 60 mV dec −1 , the average SS is from 0.82 mV dec −1 to 6.1 mV dec −1 and the maximum on-current is from 73.9 μA μm −1 to 165.2 μA μm −1 , which is one of the best reported results 17 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 (Fig. 2c ).

a , Transfer characteristics I c – V b of a transistor with a 2-μm gap showing an abruptly changing collector current I c with a minimum SS of 0.38 mV dec −1 . b , SS– I c relationship showing minimum values of SS from 0.38 mV dec −1 to 1.52 mV dec −1 and the range of the current with an SS less than 60 mV dec −1 of about 1 to 3 orders of magnitude. c , Benchmark of the average SS and maximum on-current of the transistor for a current with an SS less than 60 mV dec −1 , which is one of the best reported results when compared with impact ionization MOSFETs (I-MOS), depletion-IMOS (DIMOS), heterojunction tunnel field-effect transistors (HJ-TFET), black phosphorus tunnel field-effect transistors (BP TFET), heterojunction tunnel triodes (HJ-TTs), carbon nanotube tunnel field-effect transistors (CNT TFET) and negative-capacitance field-effect transistors (NC-FET) 17 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 . d , Transfer characteristics with temperature-dependent current behaviour. e , The critical base bias V b-critical when I c starts to increase abruptly increases linearly with V c . f , For different biases of V c , devices show increasing V b-critical with increasing gap length d gap from 5 μm to 75 μm. g , As I c increases abruptly, I e also increases abruptly. h , i , An illustration of a transistor with a gap of a length of d gap in the Gr channel ( h ) and its energy-band diagram near the Gr channel ( i ).

Stimulated emission of heated carrier mechanism

It is noted that holes are the main conduction carriers in the HOET because Gr is p-type (Extended Data Fig. 4 ), and the abrupt negative I c indicates a sudden increase in the hole current flowing out of the collector, which is neither a normal reverse leakage current of the Gr/Ge junctions nor a forward current of the base-Gr/p-Ge junction. Four phenomena shed light on the device operation mechanism. First, the transfer characteristics are temperature dependent (Fig. 2d ). Different from the tunnelling behaviour, the current changes more abruptly when the temperature increases. The ultralow SS appears when the temperature is above room temperature, which is the working temperature of most realistic systems. Second, the critical base bias V b-critical when I c abruptly changes increases linearly with V c , and V c  −  V b-critical is about 0.7 V, leading to a forward-biased base-Gr/p-Ge junction (Fig. 2e ). Third, at each bias of V c , V b-critical increases with increasing gap length d gap (5 μm to 75 μm in 5-μm steps; Fig. 2f and Extended Data Fig. 5 ). Finally, I c and I e increase abruptly at the same time (Fig. 2g ). These phenomena can be summarized as that initially both the emitter-Gr/p-Ge junction and the base-Gr/p-Ge junction are reverse biased, and when the base bias increases to a critical value, the base-Gr/p-Ge junction is sufficiently forward biased, so that an exceptional number of holes in the emitter-Gr will suddenly be emitted into the Ge collector, while holes will enter from the emitter to ensure a continuous current from the emitter to the collector. The higher the temperature, the more obvious the phenomenon, and the shorter the gap, the smaller the critical base bias.

We propose a stimulated emission of heated carrier (SEHC) mechanism to explain these phenomena using a structure illustration (Fig. 2h ) and an energy-band diagram (Fig. 2i ) of the device. There are four processes that collectively lead to the ultralow SS. In process A (carrier heating), V b and the electric field in the emitter-Gr accelerate holes there to become heated holes; however, they are not hot enough to overcome the emitter-Gr/Ge potential barrier. In process B (carrier injection), holes are injected from Ge into the base-Gr to become high-energy holes with the forward bias there. In process C (carrier diffusion), the injected high-energy holes in the base-Gr will overcome the potential barriers induced by the base-Gr/Ge/emitter-Gr structure by diffusion to arrive at the emitter-Gr. In process D (carrier emission), with a higher energy, these arrived holes will pass their energy to the heated ones in the emitter-Gr through carrier–carrier scattering (CCS) 32 , making them the stimulated carriers that will continue to participate in the CCS process, causing a stimulated-carrier multiplication. These stimulated carriers with high energy will overcome the emitter-Gr/Ge barrier with the reverse bias there, leading to an abrupt hole current ( Methods ). The Ge collector current will first increase to a peak abruptly and then decrease when the current of the base-Gr/Ge junction begins to dominate. Compact modelling is used to further explain the multiplication and emission process ( Methods and Extended Data Fig. 6 ). The SEHC mechanism indicates that even a transistor with a continuous Gr channel can still generate an ultralow SS, which is validated by our experiments (Extended Data Fig. 7 ).

Negative differential resistance

The NDR effect refers to the characteristic where the current of a device decreases as the voltage increases, which has been widely used in modern electronics such as amplifiers, microwave generators, high-frequency oscillators and high-speed digital-to-analogue converters, generally evaluated by the ratio of maximum and minimum currents, that is, the PVR 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 . However, when using Si and Ge technologies, the NDR effect generated by a hot-carrier device is limited where the PVR is no more than three 42 , 43 , 44 , 45 , 46 . In the HOET, the output characteristics I c – V c show an obvious NDR (Figs. 1e and  3a ). When the collector bias V c increases, I c first increases to a peak value, and then decreases to the reverse currents of the Gr/Ge junctions. The output characteristics are temperature dependent where the NDR gradually vanishes when the temperature decreases (Fig. 3b ), and at each bias of V b , the voltage V c-peak where I c achieves its maximum, decreases as the gap length d gap increases (Fig. 3c and Extended Data Fig. 8 ).

a , Output characteristics I c – V c of a transistor with a 3-μm gap showing the PVR. b , Temperature-dependent output characteristics. c , For different biases of V b , devices with an increasing gap length d gap from 5 μm to 75 μm show a decreasing V c-peak . d , Peak and valley currents as well as the corresponding PVR from 90.6 to 24.6 in the output characteristics. e , Benchmark of the PVR for our device compared with devices using Gr and RSTTs using Si and Ge technologies 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 . GO, graphene oxide; hBN, hexagonal boron nitride.

These phenomena are consistent with the SEHC mechanism: in the output characteristics, for each negative bias of V b , as the negative bias of V c increases, the hot holes at the emitter-Gr are collected by the collector, leading to a large negative I c , gradually reaching the peak current. When V c further increases, the bias of the base-Gr/Ge junction changes from a forward bias to a reverse one, and the carrier-injection process stops, leading to the valley current. It should be noted here that although an RSTT can also generate an NDR, the characteristics are different. In an RSTT, the NDR shows in the I b – V b curve where I b decreases as V b increases because the carriers are accelerated by V b to become hot and are transferred to the collector. In a HOET, I b never decreases, no matter how large V b is (before the device is damaged), which is also true even for a transistor with a continuous Gr channel, indicating that carriers cannot be accelerated to become hot enough only by applying V b .

The peak and valley currents increase with the base bias V b (Fig. 3d ), and the PVR is from 90.6 to 24.6 (Fig. 3d ). When V b is −3 V, the high PVR is due to a small leakage current of the Gr/Ge junction, and the best PVR is 126 (Extended Data Fig. 9 ). This result is one of the highest values for a device using Gr 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , and is higher than any RSTT using Si and Ge technologies 42 , 43 , 44 , 45 , 46 (Fig. 3e ), and is also comparable to the best result of a tunnel device using two-dimensional materials 14 .

Multi-valued logic technology

The multifunctional HOET is promising in various applications. For example, multi-valued logic (MVL) uses more than two logic states to enable rapid and low-power data processing with high-density integration 15 , and the HOET can be used to provide a high inverter gain and reconfigurable logic states for MVL, which has rarely been reported before. A circuit was fabricated using three HOETs (T1–T3) in parallel with a common emitter, a common collector (Ge substrate) and separated bases 1–3, illustrated by an equivalent circuit and device symbols (Fig. 4a,b ). The input and output signals are voltage and current, respectively 43 where the lowest voltage potential corresponds to the input logic ‘0’ and the smallest current (absolute value) corresponds to the output logic ‘0’.

a , In the circuit, three HOETs (T1, T2 and T3) are connected in parallel with a common Ti/Au emitter, a common Ge collector and separated bases. b , An equivalent circuit using device symbols showing a common emitter and collector and separated bases 1–3. c , The input (IN) and output (OUT) signals are voltage and current, respectively. As V b3 changes, three abrupt changes of I c occur, showing that the circuit is a quaternary digital logic inverter. d , The inverter gain g m (d I c /d V b3 ) can approach 1 mA μm −1  V −1 when the logic state changes. e , f , The dependence of I e on V b3 is also the behaviour of a quaternary inverter ( e ) with a high inverter gain g m (d I e /d V b3 ) ( f ). g – i , When different combinations of base biases are applied, the input logic signal V c can be linked to different output logic signal I c , leading to a ternary digital logic inverter ( g ), a ternary follower ( h ) and a component that can be used to construct an adder ( i ).

To demonstrate a high inverter gain, one base voltage is used as the input signal (IN, taking V b3 as an example), and the collector current I c is the output signal (OUT; Fig. 4c ). Other voltage biases can be applied to control the shape of the I c curve, such as the position where an abrupt change happens. As V b3 changed from 0 V to −12 V, the injected carriers from base 3 first arrived at the emitter of device T3 leading to an abrupt change of I c , followed by another two abrupt changes when the injected carriers arrived at the emitters of devices T2 and T1. The relationship between I c and V b3 demonstrates that the circuit can be seen as a quaternary (0, 1, 2, 3) digital logic inverter that has three characteristics. First, the inverter gain g m (transconductance d I c /d V b3 ) is high when the logic state changes because of the abruptly changing I c , approaching 1 mA μm −1  V −1 , which can be used to fabricate a low-power MVL (Fig. 4d ). Second, more HOETs can be connected in parallel to achieve quinary or even higher system using a simple structure. Third, the dependence of I e on V b3 is also the behaviour of a quaternary inverter, which provides more flexibility for circuit design (Fig. 4e,f ).

To demonstrate reconfigurable logic states, the output characteristics I c – V c are investigated. V c is used as the input signal (IN), and the collector current I c is the output signal (OUT). I c is the sum of the collector currents of the three HOETs. For each collector current, the position where it achieves the maximum value is controlled by its base bias. Therefore, when different combinations of base biases are applied, the logic states of the output signal are different, that is, they are reconfigurable, leading to different functions. When the input logic signal is (2, 1, 0), if the output logic signal is (0, 1, 2), the circuit is a ternary digital logic inverter (Fig. 4g ). If the output logic signal is (2, 1, 0), it is a ternary follower (Fig. 4h ). If the output logic signal is (0, 2, 1), it can be used to construct an adder (Fig. 4i ). More possibilities can be realized by using different base biases, and more HOETs can be connected in parallel to achieve higher system.

Using the SEHC mechanism based on mixed-dimensional materials, the HOET provides another member of the hot-carrier transistor family, generating an ultralow SS that is one of the lowest reported values and a PVR in the NDR effect that is one of the highest for Gr devices. By combining the correct materials and device structure, the HOET can provide a multifunctional and high-performance device with potential applications in low-power and NDR technologies for the post-Moore era.

Preparation of the substrate

A p-type (100) Ge substrate with a resistivity of 1–10 Ω cm was cleaned by hydrofluoric acid (40 wt%) for 60 s to remove native oxide on the surface. A 30-nm-thick HfO 2 insulating layer was deposited on top of the Ge substrate by atomic layer deposition at 200 °C (precursors, tetrakis (dimethylamido) hafnium (Hf (NMe 2 ) 4 ) and water). The bottom of the Ge substrate was scratched, and Ti/Au (5/50 nm) metallization was performed by electron beam evaporation to form an ohmic contact. Electrode metallization using Ti/Au (5/50 nm) on the surface was formed by photolithography and electron beam evaporation. For photolithography, photoresist s-1813 (spin-coated at 3,000 rpm for 30 s, baked at 120 °C for 2 min) and LOR3A (spin-coated at 3,000 rpm for 50 s, baked at 190 °C for 5 min) were used in sequence. The HfO 2 layer on the substrate was then patterned by photolithography and reactive ion etching (CF 4 50 standard cubic centimetres per minute (sccm), 5.0 Pa, radiofrequency power 100 W, 5.5 min), followed by dilute hydrofluoric acid (5 wt%) etching for 30 s to form a window to the Ge.

Preparation of the monolayer Gr film

Monolayer Gr film was synthesized by chemical vapour deposition on a commercial copper foil (99.9%, 25-μm thick). The copper foil was first annealed at 1,000 °C under a 5-sccm hydrogen flow and then exposed to a mixture of hydrogen (5 sccm) and methane (60 sccm) at a total pressure of 100 Pa for 30 min to grow Gr, followed by slow cooling to room temperature.

Gr film transfer and device fabrication

Gr was transferred by using the typical wet polymethyl methacrylate (PMMA) method. The solution of PMMA (950 kDa molecular weight, Sigma, 4 wt% in ethyl lactate) was first spin-coated on the graphene/Cu foil at 2,000 rpm for 60 s and cured at 180 °C for 15 min. After removing the Cu foil by chemical etching, the PMMA/Gr film was carefully collected on the desired target substrate and baked. PMMA was then removed by immersing in acetone at 50 °C to complete the transfer. Finally, the transferred Gr was patterned by photolithography and oxygen plasma etching (200 W, 180 sccm, 2 min).

The emission process in the SEHC mechanism

When the collector current increases abruptly, (A) the electric field in the emitter-Gr heats the holes there while (B) high-energy holes are injected from Ge into the base-Gr, which will arrive at the emitter-Gr by (C) diffusion. Only one injected hole is shown (Extended Data Fig. 6a ). The arrived high-energy holes will pass their energy to the heated ones through (D1) CCS 32 (Extended Data Fig. 6b ). When the stimulated holes in the emitter-Gr gain enough energy from the injected holes, (D2) a multiplication process happens (Extended Data Fig. 6c ), before the stimulated holes with enough energy are (D3) emitted into Ge with the reverse bias there, leading to the abrupt current (Extended Data Fig. 6d ).

In the CCS process, after one collision between carriers, the number of carriers that can cross the Gr/Ge barrier will double, and the energy these carriers possess after the collision is still higher than the Gr/Ge barrier. In addition, the lateral electric field generated by V b can increase these carriers’ energy. Therefore, the carriers after the collision can continue to participate in the CCS, causing the number of carriers that can cross the barrier to double again. Meanwhile, In the energy domain, the CCS will result in a high-energy-band tail in the energy distribution function, indicating an increase in high-energy carrier distribution 32 . Therefore, the continuous CCS process can cause the number of high-energy carriers in the emitter-Gr to increase repeatedly, leading to a surge in the reverse current. It should be noted that the impact ionization 47 cannot be responsible for this phenomenon, as that I c never increases abruptly no matter how large V b and the corresponding electric field is applied (before the device is damaged) in the emitter-Gr if the base-Gr/Ge junction is not forward biased.

Modelling of the CCS multiplication process

The base bias V b determines the current I c not only by providing a lateral electric field in the emitter-Gr but also by controlling the injected carriers at the base-Gr/Ge junction, leading to a complex relationship among the scattering, the multiplication and V b , and therefore a complex one between I c and V b . In fact, multiplication processes are usually modelled using an experience-based approach 47 and we provide an empirical model for the multiplication process in the HOET below.

The critical base bias V b-critical , where I c increases abruptly, increases linearly with the collector bias V c (Fig. 2e ) and the gap length d gap (Fig. 2f ). On the basis of these experimental results, I c is described as I c  =  M  ×  I rev  +  I 0 , M  =  A /(1 − ( V b  −  V c )/( V b-critical  −  V c )), V b-critical  =  Bd gap  +  V c  +  C , where I rev is the reverse current of the emitter-Gr/Ge junction before the CCS multiplication, M is the CCS multiplication factor and I 0 , A , B and C are fitting constants. As shown in Extended Data Fig. 6e , the model fits the experimental results well.

Modelling of the Gr/Ge junction

On the basis of the thermionic-emission current model of a Schottky junction, the Gr/p-Ge Schottky potential barrier height qϕ B , ideality factor η , interface state density D it and series resistance R s are estimated as follows. The relationship of the forward current I F of the Gr/Ge junction and temperature T is ln( I F / T 2 ) =  C  −  q ( ϕ B  –  V c / η )/ k  × (1/ T ), where C is a constant, q is the elementary charge, V c is the forward voltage bias and k is Boltzmann’s constant 3 . Using an Arrhenius plot, the slopes of the fitted lines – q ( ϕ B  –  V c / η )/1,000 k is plotted against V c (Extended Data Fig. 3c ), and the y intercept at 0 V is S 0  = − qϕ B /1,000 k leading to a qϕ B of about 0.38 eV, while the slope is Slope* =  q /1,000 kη leading to an η of about 1.29. D it is estimated using η and ϕ B based on a relationship of η  = 1 + ( δ / ε 0 )( ε s / W d  +  q 2 D it ), where δ is the thickness of an interfacial layer between Gr and Ge, ε 0 is the permittivity in vacuum (8.85 × 10 −14  F cm −1 ), ε s is the relative dielectric constant (16.2) of Ge and W d is the thickness of the depletion layer of Ge (ref. 3 ). W d  = (2 ε s / qN a  × ( ψ bi  −  V c  −  kT / q )) 0.5 where N a is the doping concentration of Ge (10 16  cm −3 ) and ψ bi is the built-in potential barrier height in the semiconductor as ψ bi  =  ϕ B  −  ϕ n . ϕ n  =  kT / q  × ln( N v / N a ) where N v is the effective states density of the valence band of Ge (5.7 × 10 18  cm −3 ). On the basis of these models, D it is estimated to be about 2.6 × 10 12  cm −2  eV −1 . A series resistance R s of the junction of about 3 kΩ is extracted by a linear fitting of the forward I – V characteristic at a high voltage bias (Extended Data Fig. 3d ).

Characterization

Characterization of the graphene film and the devices was performed using a confocal Raman spectrometer (Jobin Yvon Lab RAM HR800), an optical microscope (Nikon LV100ND), a scanning electron microscope (FEI XL30 SFEG using an accelerating voltage of 10 kV) and an atomic force microscope (Bruker Dimension Icon AFM). The transistors were measured using a semiconductor analyser (Agilent B1500A with a capacitance measurement unit B1500A-A20) and a probe station (Cascade Microtech 150-PK-PROMOTION) at room temperature, and a vacuum probe station (Lake Shore TTPX/TSM1D1001) at low temperature.

For device uniformity, taking the device with a 3-μm gap as an example, 20 devices were fabricated on a wafer. The transfer characteristics ( V c  = −2 V) show that for SS, sample size = 20, mean = 0.60 mV dec −1 and standard deviation = 0.29 mV dec −1 , whereas the output characteristics ( V b  = −4 V) show that for PVR, sample size = 20, mean = 15.80 and standard deviation = 2.84. The uniformity can be improved by advanced processes, such as using a Gr-on-Ge wafer where the Gr is grown directly on Ge instead of manual Gr transfer 48 .

Opportunities and challenges

The SEHC mechanism can be applied to devices composed of different materials. For example, using a carbon nanotube film/n-Ge junction, n-type HOETs can be fabricated (Extended Data Fig. 10 ). Complex circuits can be realized by using both the n-type and p-type HOETs. However, for the HOET to ultimately become practical, a series of problems must be solved including increasing the range of the current with an SS less than 60 mV dec −1 , improving the PVR in the NDR applications and reducing the hysteresis in the characteristics.

At present, although the on-current of the transistor is high, the off-current is also high, resulting in a limited current range with a SS less than 60 mV dec −1 , which is not an intrinsic result of the SEHC mechanism. The off-current should be reduced and the on-current increased to improve the on-to-off current ratio. To reduce the off-current, (1) the quality of the Gr/semiconductor interface should be improved by using a Gr-on-Ge wafer where the Gr is grown directly on Ge instead of being transferred 48 and (2) other material combinations can be used, such as Gr combined with wider-bandgap semiconductors, where the potential barrier height of the Gr/semiconductor junction is higher and the intrinsic carrier concentration in the semiconductor is lower. To increase the on-current, the energy of the carriers injected from the base-Gr should be further increased, perhaps by using asymmetric potential barriers of the base/substrate and emitter/substrate junctions, which can be achieved by using different substrate semiconductor materials under the base-Gr and the emitter-Gr. These requirements are also necessary for improving the PVR in the NDR applications.

Typical transfer and output characteristics show that the width of the hysteresis window is about 0.25 V and 0.23 V, respectively. However, it should be noted that the hysteresis is not caused by the SEHC mechanism intrinsically, but by the limited quality of the Gr/Ge interface. Because of the contamination and imperfection during the transfer and fabrication process, the Gr/Ge junction itself shows a large hysteresis. This can be reduced by using a Gr-on-Ge wafer where the Gr is grown directly on Ge instead of being transferred or by using an encapsulation.

Data availability

Relevant data are available via Zenodo at https://doi.org/10.5281/zenodo.11481313 (ref. 49 ).

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Acknowledgements

This work was supported by National Natural Science Foundation of China (grant numbers 62074150, 62125406, 52272051 and T2293703), Excellent Youth Foundation of Liaoning (2023JH3/10200003) and National Key Research and Development Program of China (2021YFA1200013). We thank P. Thrower, B. Song, Y.-P. Wang, C. Liu and Z. Han for discussions.

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These authors contributed equally: Chi Liu, Xin-Zhe Wang, Cong Shen, Lai-Peng Ma

Authors and Affiliations

Shenyang National Laboratory for Materials Science, Institute of Metal Research, Chinese Academy of Sciences, Shenyang, China

Chi Liu, Xin-Zhe Wang, Lai-Peng Ma, Xu-Qi Yang, Yue Kong, Wei Ma, Yan Liang, Shun Feng, Xiao-Yue Wang, Yu-Ning Wei, Xi Zhu, Bo Li, Chang-Ze Li, Shi-Chao Dong, Wen-Cai Ren, Dong-Ming Sun & Hui-Ming Cheng

School of Materials Science and Engineering, University of Science and Technology of China, Shenyang, China

School of Electronic and Computer Engineering, Peking University, Shenzhen, China

Cong Shen & Li-Ning Zhang

Institute of Technology for Carbon Neutrality, Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, People’s Republic of China

Hui-Ming Cheng

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Contributions

C.L., D.-M.S. and H.-M.C. conceived the project. C.L., X.-Z.W., C.S. and L.-P.M. were equal major contributors to this work. C.L. designed the device and the circuit and analysed the data. C.L., X.-Z.W., X.-Q.Y. and Y.K. performed the experiments as well as electrical measurements assisted by Y.L., S.F., Y.-N.W., X.Z., X.-Y.W., B.L. and C.-Z.L. L.-P.M., W.M. and S.-C.D. carried out graphene growth, transfer and characterization supervised by W.-C.R. C.L., C.S. and L.-N.Z. proposed the device mechanism. C.S. performed the device modelling supervised by L.-N.Z. C.L. and D.-M.S. wrote the paper. All authors discussed the results and commented on the paper.

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Correspondence to Chi Liu , Li-Ning Zhang or Dong-Ming Sun .

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Extended data figures and tables

Extended data fig. 1 characterization of the monolayer graphene film..

a Raman spectra of 10 randomly selected points on the graphene film transferred onto the SiO 2 /Si substrate. The characteristic peaks observed at about 1590 cm −1 (G band) and about 2680 cm −1 (2D band) with the I 2D  > I G and the absence of defect-induced D band (1350 cm −1 ) indicate that the film is a high-quality monolayer graphene. b Large-area HRTEM image of the graphene film (scale bar: 5 nm). The well-defined hexagonal lattice in the absence of defects and impurities confirms the high-quality of the monolayer graphene film.

Extended Data Fig. 2 I − V characteristics of transistors with biases of V b = 0 and V c = V e .

The devices use a a graphene channel with a gap and b a continuous graphene channel. When there is a gap in the graphene channel, the limited I e indicates the separation of the emitter-Gr and the base-Gr. On the other hand, when a continuous graphene channel is used, the large currents ( I e  =  I b ) are the currents in the continuous graphene channel.

Extended Data Fig. 3 I − V characteristics of the Gr/p-Ge junctions.

a The rectifying current ratio of about 10 3 at ±3 V indicates the existence of a Schottky potential barrier between graphene and Ge at room temperature. Gr was grounded and V c was applied on the Ge substrate. b I − V characteristics of the Gr-Ge junction measured at various temperatures from 224 K. c Arrhenius plots with V c from 0.084 to 0.18 V in steps of 0.012 V. Inset: The fitted slope plotted against V c , where the y-intercept at 0 V ( S 0 ) and the slope (Slope * ) gives a Schottky potential barrier height q ϕ B of 0.38 eV and an ideality factor η of 1.29 (Methods). d A series resistance of the junction of about 3 kΩ is extracted by linear fitting of the forward I − V characteristics when V c is much larger than the built-in potential barrier height ψ bi .

Extended Data Fig. 4 Investigation of the carrier type in the graphene channel.

a Correlation between the frequencies of G and 2D Raman bands of the graphene on Ge, showing a typical p-type doping without a significant strain caused by processing. 130 Raman spectra were collected for the statistical analysis of doping and strain. b Electrical methods were used to further clarify the doping type. Input characteristics I b − V b of a transistor with a continuous graphene channel was investigated. When the base bias V b is less than −1 V, a collector bias V c from −1 to −9 V leads to reverse biased emitter-Gr/Ge and base-Gr/Ge junctions. Therefore, the large I b is the conduction current in the continuous graphene channel. When V c increases, I b also increases. This can be explained by c the corresponding energy band diagram of the Gr/Ge junction with an increasing collector bias V c . When V c increases, because of the quantum capacitance effect of Gr, its Fermi-energy level will go down as shown using the blue arrow in the diagram. Only if the graphene is p-type so that the conduction carriers are holes, will the carrier concentration increase and lead to an increasing current. Therefore, in the HOET, the conduction carriers are holes.

Extended Data Fig. 5 Transfer characteristics I c − V b of HOETs.

The length of gap d gap between emitter-Gr and base-Gr increases from a 5 to o 75 μm. For each bias of V c , the critical base bias when the collector current I c starts to increase abruptly tends to increase with d gap .

Extended Data Fig. 6 Illustrations for the emission process in the stimulated emission of heated carrier mechanism.

a When the collector current increases abruptly, (A) the electric field in the emitter-Gr heats the holes there while (B) high-energy holes are injected from Ge into the base-Gr which will arrive at the emitter-Gr by (C) diffusion. b The arrived high-energy holes will pass their energy to the heated ones through (D1) carrier-carrier scattering (CCS). c After the stimulated holes in the emitter-Gr have enough energy from the injected holes, (D2) a multiplication process happens, before d the stimulated holes with enough energy are (D3) emitted into Ge with the reverse bias there, leading to the abrupt current. e The empirical model fits the experimental results well for the multiplication process in the HOET.

Extended Data Fig. 7 Illustrations and I − V characteristics of a transistor with a continuous graphene (Gr) channel.

a Illustration of the device structure. b Energy band diagram near the Gr channel in (a). The stimulated emission of heated carrier (SEHC) mechanism indicates that even a transistor with a continuous Gr channel can generate an ultra-low SS. At a critical base bias, the left part of Gr/Ge junction will remain reverse biased while the right one will become forward biased. Four similar processes cause the ultra-low SS: A (carrier heating), B (carrier injection), C (carrier diffusion) where the injected high-energy holes will arrive at the left part of Gr by diffusion either using a path in Gr or one passing through Ge, D (carrier emission). c Transfer characteristics I c − V b show a negative abruptly changing collector current I c . d Output characteristics I c − V c show an obvious negative differential resistance.

Extended Data Fig. 8 Output characteristics I c − V c of HOETs.

The length of gap d gap between emitter-Gr and base-Gr increases from a 5 to o 75 μm. For each bias of V b , the voltage where I c achieves its maximum tends to decrease as d gap increases.

Extended Data Fig. 9 An output characteristic I c − V c of a transistor with a 35-μm gap at V b = −3 V.

The peak to valley current ratio (PVR) is 126, higher than any Gr device and Si/Ge RSTT, and is comparable to the best two-dimensional tunnel device.

Extended Data Fig. 10 I − V characteristics of an n-type HOET fabricated based on CNT film/n-Ge junctions.

A 4-μm gap in the CNT film channel was formed using photolithography. a Transfer characteristics I c − V b show an abruptly changing collector current I c . Note that since electrons are the conduction carrier, the polarity of the bias is opposite to that of the p-type device. b Output characteristics I c − V c show an obvious negative differential resistance. The peak-to-valley current ratio (PVR) is higher than 18.

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Liu, C., Wang, XZ., Shen, C. et al. A hot-emitter transistor based on stimulated emission of heated carriers. Nature (2024). https://doi.org/10.1038/s41586-024-07785-3

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Received : 05 September 2023

Accepted : 04 July 2024

Published : 14 August 2024

DOI : https://doi.org/10.1038/s41586-024-07785-3

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