dissertation topics for vlsi

VLSI Research Topics Ideas [MS PhD]

List of Research Topics and Ideas of VLSI for MS and Ph.D. Thesis.

• High-throughput VLSI architecture for soft-decision decoding with ORBGRAND
• Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing
• ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture
• Evaluating the Performances of Memristor, FinFET, and Graphene TFET in VLSI Circuit Design
• VLSI mask optimization: From shallow to deep learning
• Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal
• A Novel High-Performance Hybrid Full Adder for VLSI Circuits
• PGOpt: Multi-objective design space exploration framework for large-Scale on-chip power grid design in VLSI SoC using evolutionary computing technique
• Testing single via related defectsin digital VLSI designs
• An Improved Impulse Noise Removal VLSI Architecture Using DTBDM Method
• VLSI Implementation of Multi-channel ECG Lossless Compression System
• A Scalable VLSI Architecture for Illumination-Invariant Heterogeneous Face Recognition
• Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support
• Compact 3D Thermal Model for VLSI and ULSI Interconnect Network Reliability Verification
• Simultaneous Parametric and Functional Testing of Digital VLSI During Radiation Experiments
• A New 4-2 Compressor for VLSI Circuits and Systems
• An ultra-low-power CNFET-based improved Schmitt trigger design for VLSI sensor applications
• Performance Analysis of Clock Gating Designs in Low Power Vlsi Circuits
• Flexible scheme for reconfiguring 2D mesh-connected VLSI subarrays under row and column rerouting
• A Survey on VLSI Implementation of AES Algorithm with Dynamic S-Box
• High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND
• Methods for Ensuring Full Traceability of the Production Testing Results of the Digital VLSI
• Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology
• Fast Auto-Correction algorithm for Digital VLSI Circuits
• Review of VLSI Architecture of Cryptography Algorithm for IOT Security
• The VLSI Realization of Sign-Magnitude Decimal Multiplication Efficiency
• Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications
• VLSI design of a fast one-stage independent component extracting system based on ICA-R algorithm
• Fully Reused VLSI Architectu Encoding for DSRC Applica
• VLSI Architecture for DWT using 5/3 Wavelet Coefficient using Vedic Math’s
• Design and vlsi implementation of a decimation filter for hearing aid applications
• Analysis and Comparison of Leakage Power Reduction Techniques for VLSI Design
• A low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system
• Study and Analysis of Digital Counters for VLSI Applications
• Synthesis of VLSI Structural Cell Partitioning Using Genetic Algorithm
• VLSI Architecture for 8-bit Reversible Arithmetic Logic Unit based on Programmable Gate
• Features of Designing Digital Processing Systems for Radiolocation Systems Based on Microprocessor VLSI Sets
• Multiple-Criteria Decision Analysis Using VLSI Global Routing
• Performance Evaluation of VLSI Implemented WSN Algorithms
• Soft Error Rate Estimation of VLSI Circuits
• Wave pipelined VLSI architecture for a Viterbi decoder using self reset logic with 0.65 nm technology
• Efficient Band Offset Calculation Method for HEVC and Its VLSI Implementation
• 2021 IEEE 39th VLSI Test Symposium (VTS)
• A spike based learning neuron in analog VLSI
• Computing Orientation of an Image by Projection Method and its VLSI Implementation
• A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
• The First Ge Nanosheets GAAFET CMOS Inverters Fabricated by 2D Ge/Si Multilayer Epitaxy, Ge/Si Selective Etching
• Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure
• Back-Gate Network Extraction Free from Dynamic Self-Heating in FD SOI
• Improvement of Nanotwinned Copper Thermal Stability for High Temperature Heterogeneous Integration
• DFT Models of Ferroelectric Hafnium-Zirconium Oxide Stacks With and Without Dielectric Interlayers
• Selective Area Epitaxy of Axial Wurtzite-InAs Nanowire on InGaAs NW by MOCVD
• Calculation of Field Dependent Mobility in MoS2 and WS2 with Multi-Valley Monte Carlo Method
• Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density
• Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering
• On-Wafer Electronic Layer Detectors Array (ELDA) for e-beam Imaging in Advanced Lithographic Systems
• Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage
• Quantum Tunneling PUF: A Chip Fingerprint for Hardware Security
• Ferroelectric and Antiferroelectric Hf/Zr oxide films: past, present and future
• An Approach to Diminish the Leakage Power in Complementary MOS VLSI Circuits
• Benchmarking the Performance of Heterogeneous Stacked RRAM with CFETSRAM and MRAM for Deep Neural Network Application Amidst Variation and Noise
• Multi-bit cryogenic flash memory on Si/SiGe and Ge/GeSi heterostructures
• Tensor-Centric Processor Architecture for Applications in Advanced Driver Assistance Systems
• Evaluation de la complexit d’implantation en VLSI par la synth se architecturale: une exp rience en filtrage adaptatif
• A precise debugging method and defect diagnosis with mass big-data analysis in the designed high-dense array for rapid yield improvement in a logic platform
• Dynamic Mapping Mechanism to Compute DNN Models on a Resource-limited NoC Platform
• Bandgap-Engineered Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Devices
• Reconfigurable Database Processor for Query Acceleration on FPGA
• Holistic and In-Context Design Flow for 2.5 D Chiplet-Package Interaction Co-Optimization
• ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design
• Quantum dot celluar automata-based encoder and priority encoder circuits: Low latency and area efficient design
• Shutdown mode implementation for Boost and Inverting Buck-Boost converter
• AN ELEGANCE OF A NOVEL DIGITAL FILTER USING MAJORITY LOGIC FOR SNR IMPROVEMENT IN SIGNAL PROCESSING
• Recent Progress on Flexible Capacitive Pressure Sensors: From Design and Materials to Applications
• Prototypage d’algorithmes adaptatifs par un outil de synthèse d’architectures VLSI.
• ALGORITMOS PARA PROBLEMAS DE STEINER COM APLICAÇÕES EM PROJETO DE CIRCUITOS VLSI
• An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM
• Prospective incorporation of booster in carbon interconnects for high-speed integrated circuits
• Laser beam testing of finished integrated circuits
• A survey of in-spin transfer torque mram computing
• Oxytocin modulates neural processing of mitral/tufted cells in the olfactory bulb
• Power Efficient Bit Lines: A Succinct Study
• Introduction: Soft Error Modeling
• Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation
• Adiabatic Logic-Based Area-and Energy-Efficient Full Adder Design
• Improved Noise Margin and Reduced Power Consumption in Subthreshold Adiabatic Logic Using Dual Rail Power Supply
• IMPROVING SIZE-BOUNDS FOR SUBCASES OF SQUARE-SHAPED SWITCHBOX ROUTING
• Design and Performance Evaluation of Highly Efficient Adders in Nanometer Technology
• Qualitative and quantitative analysis of parallel-prefix adders
• 4-Bit Ripple Carry Adder Using Area-Efficient Full Adder in CMOS Technology
• Systolic-Architecture-Based Matrix Multiplications and Its Realization for Multi-Sensor Bias Estimation Algorithms
• BiPart: a parallel and deterministic hypergraph partitioner
• Dealing with Aging and Yield in Scaled Technologies
• Ultraefficient imprecise multipliers based on innovative 4: 2 approximate compressors
• A Low Power Approach for Designing 12-Bit Current Steering DAC
• Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization
• Gain-Cell Embedded DRAM Under Cryogenic Operation–A First Study
• Communication and performance evaluation of 3-ary n-cubes onto network-on-chips
• A New Function Mapping Approach in Defective Nanocrossbar Array Using Unique Number Sequence
• Design, Simulation and Comparative Analysis of Performance Parameters of a 4-bit CMOS based Full Adder Circuit using Microwind and DSch at Various …
• A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems
• Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit
• Carver Mead:” It’s All About Thinking,” A Personal Account Leading up to the First Microwave Transistor
• Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller
• An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder
• Advanced Silicon & Semiconducting Silicon-Alloy Based Materials & Devices
• A Novel Modeling-Attack Resilient Arbiter-PUF Design
• Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links
• Parallel algorithms
• Transistor self-heating: The rising challenge for semiconductor testing
• Adaptive Forward Body Bias Voltage Generator
• PVT Aware Analysis of ISCAS C17 Benchmark Circuit
• Hard-to-Detect Fault Analysis in FinFET SRAMs
• Design and comparative analysis of on-chip sigma delta ADC for signal processing applications
• Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs
• Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems
• Impact of Spacers in Raised Source/Drain 14 nm Technology Node InGaAs-nFinFET on Short Channel Effects
• High Speed Energy Efficient Multiplier Using 20nm FinFET Technology
• Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits
• Design and Analysis of 10T SRAM Cell with Stability Characterizations
• Evaluation of Real-Time Embedded Systems in HILS and Delay Issues
• Implementation and Analysis of Low Power Consumption Full Swing GDI Full Adders
• A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory
• [HTML][HTML] X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution
• A New Improved V-Square-Controlled Buck Converter With Rail-to-Rail OTA-Based Current-Sensing Circuits
• A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n-and p-type Flip-Flops
• Variability Analysis of On-Chip Interconnect System Using Prospective Neural Network
• Low Power NAND Gate–based Half and Full Adder/Subtractor Using CMOS Technique
• Synchronization of mutual coupled fractional order one-sided lipschitz systems
• Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders
• Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme
• High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register
• High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone
• Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique
• Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator
• Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V
• Machine-learning-based self-tunable design of approximate computing
• A novel current-controlled memristor-based chaotic circuit
• Performance Analysis of MoS2FET for Electronic and Spintronic Application
• Asynchronous Four-Phase and Two-Phase Circuits: Testing and Design for Testability
• Controlling GIDL Using Core–Shell Technique in Conventional Nano-Wire
• New FDNR and FDNC Simulation Configurations Using Inverted VDDIBAs
• Optimal Mappings of the Spectrum of BPSK/QPSK Sequences to Finite Polynomial Fields and Rings
• Impact of Multi-Metal Gate Stacks on the Performance of ß-Ga2O3 MOS Structure
• On the Reliability of In-Memory Computing: Impact of Temperature on Ferroelectric TCAM
• Design of Prominent Single-Precision 32-Bit Floating-Point Adder Using Single-Electron Transistor Operating at Room Temperature
• HIPER: Low Power, High Performance and Area-Efficient Hardware Accelerators for Hidden Periodicity Detection using Ramanujan Filter Banks
• A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation
• Design of a new BUS for low power reversible computation
• Controlling Mode Transition Noise Occurred at Ground Rail in Data Preserving MTCMOS Shift Register
• Diversity Schemes in Multi-hop Visible Light Communications for 6G Networks
• Fabrication of Micro-Compliant Mechanisms Using Micro-Stereolithography
• A 27S/32S DC-balanced line coding scheme for PAM-4 signaling
• Game Theory-based Parameter-Tuning for Path Planning of UAVs
• A Low Latency Stochastic Square Root Circuit
• New Resistorless FDNR Simulation Configuration Employing CDDITAs
• An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0 V
• Improved Store-Carry-Forward Scheme for Information Dissemination in Unfavorable Vehicular Distribution
• Effect of surface modification treatment on top-pinned MTJ with perpendicular easy axis
• Design and Implementation of an Efficient Mixed Parallel-Pipeline SAD Architecture for HEVC Motion Estimation
• Negative Voltage Generator and Current DAC Based Regulator For Flash Memory
• A non-autonomous chaotic system with no equilibrium
• SIXOR: Single-Cycle In-Memristor XOR
• Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
• Towards energy-efficient STT-MRAM design with multi-modes reconfiguration
• HT-IWT-DCT-Based Hybrid Technique of Robust Image Watermarking
• GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits
• Performance Evaluation of Sub 5 nm GAA NWMBCFET using Silicon Carbide Source/Drain Material
• A novel ultra-low power 7T full adder design using mixed logic
• Reversible Fade Gate as Decoder, Encoder and Full Adder
• A novel parallel prefix adder for optimized Radix-2 FFT processor
• Smart Soldier Health Monitoring System Incorporating Embedded Electronics
• Theoretical Analysis of Defected Ground Multiband Rectangular Shape Microstrip Patch Antenna
• Design of Efficient Ternary Subtractor
• Novel CDDITA-Based-Grounded Inductance Simulation Circuits
• Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation
• Ferroelectric HfO2 Memory Transistors with High-? Interfacial Layer and Write Endurance Exceeding 1010 Cycles
• Design and Analysis of Low-Power SRAM
• High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic
• Selective Flip-Flop Optimization for Circuit Reliability
• Effect of Developer Temperature on Photoresist Contrast in Grayscale Lithography
• Power Series Representation Op logical Functions and its Applications to Error Detection and Error Correction Codes.(Dept. E)
• Creating Fastest Self timing Reference Path for High Speed Memory Designs
• Blockchain-enabled traceable, transparent transportation system for blood bank
• Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System
• Enhancement of ovonic threshold switching characteristics using nanometer-scale virtual electrode formed within ultrathin hafnium dioxide interlayer
• Neural networks integrated circuit with switchable gait pattern for insect-type microrobot
• Analog and Radio-Frequency Performance of Hetero-Gate-Dielectric FD SOI MOSFET in Re-S/D Technology
• Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications
• Field-free and sub-ns magnetization switching of magnetic tunnel junctions by combining spin-transfer torque and spin–orbit torque
• Fundamentals of microelectronics
• Comparative Analysis of Channel Estimation Techniques in Vehicular Communication
• Statistical analysis of vehicle detection in the ITS application for monitoring the traffic and road accident using internet of things
• 3-D CMOS chip stacking for security ICs featuring backside buried metal power delivery networks with distributed capacitance
• Sensor Localization in WSNs Using Rotating Directional-Antenna at the Base Station
• A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications
• FPGA implementation of fast digital FIR and IIR filters
• Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets Using Double Ge0.95Sn0.05 Caps by Highly Selective Isotropic Dry Etch
• A 3–7 GHz CMOS Power Amplifier Design for Ultra-Wide-Band Applications
• Fault-tolerant hamiltonian cycles and paths embedding into locally exchanged twisted cubes
• Error-Controlling Technique in Wireless Communication
• Human Action Recognition Using a New Hybrid Descriptor
• Minimization of Peak-to-Average Power Ratio in DHT Precoded OFDM System by A-Law Companding
• Machine Learning Oriented Dynamic Cost Factors-Based Routing in Communication Networks
• Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning
• Physical synthesis for advanced neural network processors
• A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition
• On the Best-Partition Communication Complexity
• IMPLEMENTATION OF DIVISION AND SQUARE ROOT: MODELING AND EVALUATIONS
• Structural and Optical Analysis of Bulk-Hetero Interface Between MoS2: Pentacene
• Realization of a Low Profile, Wideband Omni-directional Antenna for Ku-band Airborne Applications
• Ultracompact channel add-drop filter based on single multimode nanobeam photonic crystal cavity
• Structural and Optical Characterization of EZO Thin Film for Application in Optical Waveguide
• Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm
• A Survey of Semantic Segmentation on Biomedical Images Using Deep Learning
• PAPR Reduction in OFDM for VLC System
• A Survey on Proactive and Reactive Channel Switching Techniques in Cognitive Radios
• FPGA-based Hardware Acceleration for SVM Machine Learning Algorithm
• Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy
• A Multichannel Link-Layer Cooperation Protocol (MLCP) for Cognitive Radio Ad Hoc Network
• AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction
• Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling
• A PVT aware differential delay circuit and its performance variation due to power supply noise
• A Survey on Methodologies and Database Used for Facial Emotion Recognition
• A Survey Study of Diseases Diagnosed Through Imaging Methodology Using Ultrasonography
• Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
• MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept
• Automated Simulator for the Validation of Bio-Impedance Devices
• The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems
• An Optimal Design of 16 Bit ALU
• Analysis of Power Adaptation Techniques Over Beaulieu-Xie Fading Model
• Design and Analysis of Wearable Step-Shaped Sierpinski Fractal Antenna for WBAN Applications
• ASSURE: RTL Locking Against an Untrusted Foundry
• Design of Dynamic Induction Charging Vehicle for Glimpse of Future: Cutting Down the Need for High-Capacity Batteries and Charging Stations
• Performance Analysis of Speck Cipher Using Different Adder Architectures
• A Comparative Analysis of Statistical Model and Spectral Subtractive Speech Enhancement Algorithms
• Dimensionality Reduction Using Principal Component Analysis for Lecture Attendance Management System
• Design and implementation of current mode circuit for digital modulation
• SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator
• A Compact IPD Based on-Chip Bandpass Filter for 5G Radio Applications
• An automated parallel simulation flow for cyber-physical system design
• Conformal Omni Directional Antenna for GPS Applications
• Recognition of Natural and Computer-Generated Images Using Convolutional Neural Network
• SPIDER-based out-of-order execution scheme for Ht-MPSOC
• Fast Encoding Using X-Search Pattern and Coded Block Flag Fast Method
• Design and Simulation of a Dual-Band Radiometer for Humidity and Temperature Profiling
• Voice Controlled IoT Based Grass Cutter Powered by Solar Energy
• Periodic Octagon Split Ring Slot Defected Ground Structure for MIMO Microstrip Antenna
• COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing
• Design of Electronic Instrumentation for Isotope Processing
• Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution
• Design and analysis of improved high-speed adaptive filter architectures for ECG signal denoising
• Compact and efficient structure of 8-bit S-box for lightweight cryptography
• Virtually Doped Silicon-on-Insulator Junctionless Transistor for Reduced OFF-State Leakage Current
• Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory Banks
• [HTML][HTML] Design and simulation of high-performance 2: 1 multiplexer based on side-contacted FED
• Special Session–Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits
• Enhancement of magnetic coupling and magnetic anisotropy in MTJs with multiple CoFeB/MgO interfaces for high thermal stability
• Nonlinear Circuits and Systems with Memristors: Nonlinear Dynamics and Analogue Computing via the Flux-Charge Analysis Method
• The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising
• Information Theory-Based Defense Mechanism Against DDOS Attacks for WSAN
• TxSim: Modeling training of deep neural networks on resistive crossbar systems
• Automated Observability Analysis for Mixed-Signal Circuits
• Silicon-on-nothing electrostatically doped junctionless tunnel field effect transistor (son-ed-jltfet): A short channel effect resilient design
• Fault Detection and Classification in Microgrid Using Wavelet Transform and Artificial Neural Network
• [HTML][HTML] Development of neural networks chip generating driving waveform for electrostatic motor
• Computer Laboratory
• Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing
• Recent Development in Analytical Model for Graphene Field Effect Transistors for RF Circuit Applications
• Phenomenological CNN model of a somatosensory effects
• Reusability and Scalability of an SoC Testbench in Mixed-Signal Verification—The Inevitable Necessity
• Power-and area-optimized high-level synthesis implementation of a digital down converter for software-defined radio applications
• 3–21 GHz broadband and high linearity distributed low noise amplifier
• 64-GHz datapath demonstration for bit-parallel SFQ microprocessors based on a gate-level-pipeline structure
• Resynthesize Technique for Soft Error-Tolerant Design of Combinational Circuits
• FPGA implementations for data encryption and decryption via concurrent and parallel computation: A review
• Vertically integrated computing labs using open-source hardware generators and cloud-hosted FPGAs
• Fast shared-memory streaming multilevel graph partitioning
• Comparison of NMOS and PMOS Input Driving Dynamic Comparator in 45nm Technology
• Hybrid Forecasting Model Based on Nonlinear Auto-Regressive Exogenous Network, Fourier Transform, Self-organizing Map and Pattern Recognition Model for Hour …
• Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency
• Design of Low Power Barrel Shifter Architecture by Using Proposed MUX Based CORDIC in CMOS Logic
• Adaptive filtering algorithms in acoustic echo cancellation: a case study in architecure complexity evaluation
• Performance improvement of elliptic curve cryptography system using low power, high speed 16× 16 Vedic multiplier based on reversible logic
• Density Gradient Study on Junctionless Stack Nano-Sheet with Stack Gate Oxide for Low Power Application
• All-digital built-in self-test scheme for charge-pump phase-locked loops
• FPGA Hardware Acceleration of Soft Error Rate Estimation of Digital Circuits
• Power-aware hold optimization for ASIC physical synthesis
• Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits
• New LMI Criterion to the Robust Stability of Discrete-Time Systems with Time-Varying Delays and Generalized Overflow Nonlinearities
• A dual-mode successive approximation register analog to digital converter to detect malicious off-chip power noise measurement attacks
• FPGA Design of SAR Type ADC Based Analog Input Module for Industrial Applications
• Secure energy efficient network priority routing protocol for effective data collection and key management in dynamic WSNs
• A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture
• Monolithic 3D stacked multiply-accumulate units
• Guidance-based improved depth upsampling with better initial estimate
• Circuit and system-level aspects of phase change memory
• An Active, Low-Power, 10Gbps, Current-based Transimpedance Amplifier in a Broadband Optical Receiver Front-End
• Conception de deux points mémoire statiques CMOS durcis contre l’effet des aléas logiques provoqués par l’environnement radiatif spatial
• Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits. Electronics 2021, 10 …
• A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices
• Design and Fabrication of a Polymer Microring Resonator: Polymer Microring Resonator
• Design for Testability of Low Dropout Regulators
• Magnonic band structure in CoFeB/Ta/NiFe meander-shaped magnetic bilayers
• Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic
• Higher-order Network Analysis Takes Off, Fueled by Classical Ideas and New Data
• High-Level Synthesis of Custom DSP Blocks using Distributed Arithmetic
• Enhancement-Mode Atomic-Layer-Deposited In2O3 Transistors With Maximum Drain Current of 2.2 A/mm at Drain Voltage of 0.7 V by Low-Temperature Annealing …
• Design of High-Speed Binary Counter Architecture for Low-Power Applications
• A Systematic Review on an Embedded Web Server Architecture
• Build-in compact and efficient temperature sensor array on field programmable gate array
• SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level
• Low power, high-performance reversible logic enabled CNTFET SRAM cell with improved stability
• Design and Verification of Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol
• A Reconfigurable Architecture to Implement Linear Transforms of Image Processing Applications
• Etude du bruit électrique en 1/f et des fluctuations RTS aux basses fréquences dans le transistor MOS submicronique
• sonal communication, June 16, 1994.
• In-memory realization of SHA-2 using ReVAMP architecture
• Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM
• Design and validation of an artificial neural network based on analog circuits
• Insight into threshold voltage and drain induced barrier lowering in negative capacitance field effect transistor
• The past and future of multi-gate field-effect transistors: Process challenges and reliability issues
• A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS……………….. K. Shiba …
• [HTML][HTML] A Survey on Application Specific Processor Architectures for Digital Hearing Aids
• A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era
• Multilevel Hypergraph Partitioning with Vertex Weights Revisited
• [HTML][HTML] The involution tool for accurate digital timing and power analysis
• Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency. Electronics 2021, 10, 71
• Memristor based high speed and low power consumption memory design using deep search method
• Comparative Analysis of Adder for Various CMOS Technologies
• Design of Parallel Sorting System Using Discrete-Time Neural Circuit Model
• Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits
• Process Variation-Aware Soft Error Rate Estimation Method for Integrated Circuits
• Global placement with deep learning-enabled explicit routability optimization
• Microcomputer Application in Motion Control
• Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip
• Capacitance-to-Digital Converter for Operation under Uncertain Harvested Voltage down to 0.3 V with No Trimming, Reference and Voltage Regulation
• Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications
• A Theoretical Study of Design Rewiring Using ATPG
• FPGA Implementation of Bio-inspired Computing Based Deep Learning Model
• Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators
• Employing the Empirical Mode Decomposition to Denoise the Random Telegraph Noise
• Dependence of metal gate work function variation for various ferroelectric thickness on electrical parameters in NC-FinFET
• [HTML][HTML] A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs
• Electronically tunable third-order dual-mode quadrature sinusoidal oscillators employing VDCCs and all grounded components
• FPGA Implementation of Radix-4-Based Two-Dimensional FFT with and Without Pipelining Using Efficient Data Reordering Scheme
• TRENDS IN DISTRIBUTED OBJECT COM-PUTING
• Designing a New 4: 2 compressor using an efficient multi-layer full-adder based on nanoscale quantum-Dot cellular automata
• Introduction to Dual Mode Logic (DML)
• 3-D IC: An Overview of Technologies, Design Methodology, and Test Strategies
• A Novel Plaintext-Related Color Image Encryption Scheme Based on Cellular Neural Network and Chen’s Chaotic System
• Spatial Coverage of FM Radio Signal Variation Measurement and Comparison of two Major Radio Stations within Akwa Ibom State
• Fabrication and selective wet etching of Si0. 2Ge0. 8/Ge multilayer for Si0. 2Ge0. 8 channel gate-all-around MOSFETs
• High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber on FPGAs
• Dynamic workload allocation for edge computing
• Non-volatile memory behavior of interfacial InOx layer in InAs nano-wire field-effect transistor for neuromorphic application
• A Case Study on FPGA Implementation of Parts Counting Orientation Recognition Method for Industrial Vision System
• A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth
• A low-power dynamic ternary full adder using carbon nanotube field-effect transistors
• Design and analysis of (5, 10) regular LDPC encoder using MRP technique
• Low-Voltage DML
• Efficient Ternary Compressor Design Using Capacitive Threshold Logic in CNTFET Technology
• Realization of 8 x 4 Barrel shifter with 4-bit binary to Gray converter using FinFET for Low Power Digital Applications
• Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm
• High-speed programmable photonic circuits in a cryogenically compatible, visible-NIR 200 mm CMOS architecture
• S ntese de Alto N vel de Protocolos para a Abordagem IP sobre ATM
• A Systematic Review of Approximate Adders: Accuracy and Performance Analysis
• Evaluation of low power consumption network on chip routing architecture
• Tiny robots and sensors need tiny batteries—here’s how to do it
• Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation
• Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications
• Gradual magnetization switching via domain nucleation driven by spin–orbit torque
• TEM studies during development of a 4-megabit DRAM
• Circuit Design Using Genetic Programming: An Illustrative Study
• Machine Learning for Electronic Design Automation: A Survey
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Computer Science Research Topics – MS PhD

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Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System

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The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. … continued below

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Aluru, Gunasekhar May 2016.

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• Aluru, Gunasekhar
• Mohanty, Saraju P. Major Professor
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• Sweany, Philip H.
• University of North Texas Publisher Info: www.unt.edu Place of Publication: Denton, Texas

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• Name: Master of Science
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• Department: Department of Computer Science and Engineering
• College: College of Engineering
• Discipline: Computer Engineering
• PublicationType: Master's Thesis
• Grantor: University of North Texas

The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.

• EDA or CAD system
• Electric VLSI Design System
• analog designs
• digital designs
• layout design
• open-source EDA tool
• physical verification

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• Electronic circuit design -- Data processing.
• Integrated circuits -- Very large scale integration.
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Aluru, Gunasekhar. Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System , thesis , May 2016; Denton, Texas . ( https://digital.library.unt.edu/ark:/67531/metadc849770/ : accessed September 29, 2024 ), University of North Texas Libraries, UNT Digital Library, https://digital.library.unt.edu ; .

Often people ask me to provide some pointers for project ideas in VLSI. Here, I would like to pen down some of the discussions I had done with few students in the past and make it applicable to broader audience. VLSI is a very vast domain and you can put anything as research. Having said that, VLSI can be classified under multiple major categories like 1. Accelerator design (Simulation or emulation) 2. EDA algorithm development or improvement using machine learning 3. Backend -physical implementation or design rule optimization using machine learning 4. STA simplification and DFT. 5. High performance Transistor designing and modelling 6. Fabrication - Material design and equipment design for manufacturing Each of the above ones have large number of applications and problems that are unsolved and a lot of researchers working on these areas. Some specific ideas include : 1. Better architecture for enhanced bus arbitration to reduce cache miss rate or optimal dataflow for scratchpad memory accesses. 2. Reducing time complexity or improving accuracy of EDA tool using machine learning algorithms or development of the EDA tools for latest technology node or new material or fabrication technique. 3. DRC/CDC automation to check quality and also improvise congestion in full chip 4. Timing optimization for DFT implementation (Lot of time is spent on checking quality of chip post fabrication) 5. 5G needs high throughput, low power, high frequency transistors that require heterogeneous compounds with Silicon material. Study on materials and its iteration is required. 6. Packaging is a challenge with the emerging multi-chip, multi-stack designs. What materials and design structures to use? Here, I provided set of examples in each categories. Several research work is currently on-going and can be studied from ISPASS, VLSI, and other conferences.

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• Low Power VLSI Design

Review Paper on Low Power VLSI Design Techniques

• August 2014
• International Journal of Electrical and Computer Engineering (IJECE) 1(4):14-18

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The IEEE Circuits and Systems Society is the leading organization that promotes the advancement of the theory, analysis, computer-aided design and practical implementation of circuits, and the application of circuit theoretic techniques to systems and signal processing. The Society brings engineers, researchers, scientists and others involved in circuits and systems applications access to the industry’s most essential technical information, networking opportunities, career development tools, and many other exclusive benefits. 

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The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premiere forum for researchers in the active fields of theory, design and implementation of circuits and systems. This is accomplished through technical conference sessions, poster sessions, live demonstration sessions, and publication of conference papers. ISCAS 2024 is inspired by the theme "circuits and systems for sustainable development", which is perfectly aligned with the host city's goal.

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2024 ifip/ieee 32nd international conference on very large scale integration, 2024 ieee international symposium on integrated circuits and systems.

IEEE Transactions on Very Large Scale Integration Systems

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems  covers design and realization of microelectronic systems using VLSI/ULSI technologies that require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

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Editor-in-chief, mircea r. stan, associate editor-in-chief, associate editor tvlsi, magdy abadir, tughrul arslan, amine bermak, chye chirin boon, andreas burg, chip hong chang, meng-fan (marvin) chang, yao-wen chang, yong (nick) chen, paolo s. crovetti, josé pineda de gyvez, raffaele de rose, shiro dosho, rolf drechsler, ibrahim (abe) elfadel, xuanyao (kelvin) fong, masanori hashimoto, deukhyoun heo, tsung-yi ho, houman homayoun, yuh-shyan hwang, rajiv joshi, tanay karnik, chulwoo kim, tony tae-hyoung kim, seok-bum ko, jaydeep kulkarni, volkan kursun, yoonmyung lee, hai (helen) li, longyang lin, prabhat mishra, baker mohammad, mehran mozaffari kermani, makoto nagata, mahdi nikdast, partha p pande, bipul c. paul, vasilis pavlidis, khaled n salama, patrick schaumont, fabio sebastiano, anirban sengupta, mingoo seok, vaishnav srinivas, ioannis l. syllaios, armin tajalli, mark tehranipoor, aida todri-sanial, marian verhelst, valerio vignoli, xiaoqing wen, kaiyuan yang, zhengya zhang, mark zwolinski, editorial assistant, stacey weber jackson.

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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section " Circuit and Signal Processing ".

Deadline for manuscript submissions: closed (15 November 2022) | Viewed by 14806

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The focus of this Special Issue is on the research challenges related to the design of emerging microelectronics and VLSI circuits and related systems that meet the demanding specifications of innovative applications. This Special Issue considers challenges in the fields of low power consumption, small integration areas, testing and security, without, however, being limited to them. Authors are encouraged to submit works related to emerging research topics and applications, such as hardware security, low-power IoT devices, high-performance processing cores, etc.

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VLSI Projects

Get started with your final year engineering projects with us. We are creators of a unique and innovative project Making platform for engineering students, which helps them to gain the real time experience and get the creative mind as well. We offer highly skilled VLSI and Matlab projects for engineering students. We are committed to providing the best VLSI projects and bridging the gap between academic and practical exposure within the engineering students and making them best engineer’s.

IEEE Projects for VLSI 2023 – 2024 Titles

Explore the latest IEEE VLSI projects and Machine Learning Projects for students and researchers. Our wide range of topics includes design and implementation of digital circuits, low power VLSI, FPGA and ASIC design, VLSI testing and verification, and more. Learn and advance your skills with our comprehensive project descriptions and resources.

IXV01	High Speed	COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing
IXV02	High Speed	Efficient Error Estimation for High-Level Design Space Exploration of Approximate Computing Systems
IXV03	Area Efficient	RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems
IXV04	Low Power	Physical Attack Protection Techniques for IC Chip Level Hardware Security
IXV05	Low Power	VLSI Design of Saturation-Based Image Dehazing Algorithm
IXV06	Memory	Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS
IXV07	High Speed	A Real-Time Object Detection Processor With xnor-Based Variable-Precision Computing Unit
IXV08	High Speed	Energy-Efficient Wide-Range Level Shifter With a Logic Error Detection Circuit
IXV09	Low Power	Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer
IXV10	Low Power	AxPPA: Approximate Parallel Prefix Adders
IXV11	High Speed	Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse
IXV12	High Speed	FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization
IXV13	Low Power	ACBN: Approximate Calculated Batch Normalization for Efficient DNN On-Device Training Processor
IXV14	VLSI Communication	A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells
IXV15	Area Efficient	Approximate Softmax Functions for Energy-Efficient Deep Neural Networks
IXV16	Low Power	A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation
IX17	Testing	Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process
IX18	Low power	A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
IXV19	High Speed	A Low-Power PPG Processor for Real-Time Biometric Identification and Heart Rate Estimation
IXV20	VLSI Communication	ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture
IXV21	Machine Learning	Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM
IXV22	Area Efficient	A High-Performance Dual-Context MQ Encoder Architecture Based on Extended Lookup Table
IXV23	Low Power	A Triple Burst Error Correction Based on Region Selection Code
IXV24	Area Efficient	Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS
IXV25	High Speed	A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler
IXV26	Area Efficient	Improvement of Accuracy of Fixed-Width Booth Multipliers Using Data Scaling Technology
IXV27	Low Power	Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing
IXV26	Area Efficient	An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD
IXV27	Low Power	A Fully Integrated FVF LDO With Enhanced Full-Spectrum Power Supply Rejection
IXV28	Low Power	Startup Time and Energy-Reduction Techniques for Crystal Oscillators in the IoT Era
IXV29	Area Efficient	Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance
IXV30	Low power	A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
IXV31	Area Efficient	An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth

PREVIOUS YEAR PROJECTS

IXV1	MEMORY	Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation
IXV2	DIGITAL	A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
IXV3	DIGITAL	Hybrid LUT/Multiplexer FPGA Logic Architectures
IXV4	LOWPOWER	A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational and Sequential Circuits
IXV5	LOWPOWER	Low-Power Variation-Tolerant Nonvolatile Lookup Table Design
IXV6	LOWPOWER	Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
IXV7	DIGITAL	Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators
IXV8	DELAYLESS	High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
IXV9	DELAYLESS	A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO
IXV10	AREA BASED	A High Throughput List Decoder Architecture for Polar Codes
IXV11	DSP	Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors
IXV12	DSP	Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device
IXV13	DSP	Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks
IXV14	DELAYLESS	A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
IXV15	ANALOG	A Cellular Network Architecture With Polynomial Weight Functions
IXV16	DSP	Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
IXV17	ANALOG	Graph-Based Transistor Network Generation Method for Super gate Design
IXV18	DELAYLESS	Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
IXV19	DSP	LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
IXV20	ARITHMATIC	High-Performance NB-LDPC Decoder With Reduction of Message Exchange
IXV21	ARITHMATIC	High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2 )
IXV22	LOWPOWER	Implementing Minimum-Energy-Point Systems with Adaptive Logic
IXV23	DIGITAL	A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory
IXV24	AREA BASED	Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers
IXV25	DIGITAL	One-Cycle Correction of Timing Errors in Pipelines with Standard Clocked Elements
IXV26	DSP	Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications with Convolution Codes		BASEPAPER
IXV27	ARITHMATIC	A Mixed-Decimation MDF Architecture for Radix-2 Parallel FFT		BASEPAPER
IXV28	DELAYLESS	Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order		BASEPAPER
IXV29	AREA BASED	A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding		BASEPAPER
IXV30	ARITHMATIC	Code Compression for Embedded Systems Using Separated Dictionaries		BASEPAPER
IXV31	ANALOG	A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling		BASEPAPER
IXV32	DELAYLESS	High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels		BASEPAPER
IXV33	DELAYLESS	A High-Speed FPGA Implementation of an RSD-Based ECC Processor		BASEPAPER
IXV34	LOWPOWER	Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units		BASEPAPER
IXV35	LOWPOWER	Low-Power FPGA Design Using Memoization-Based Approximate Computing		BASEPAPER
IXV36	AREA BASED	A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography		BASEPAPER
IXV37	LOWPOWER	Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia		BASEPAPER
IXV38	DIGITAL	RF Power Gating: A Low-Power Technique for Adaptive Radios		BASEPAPER
IXV39	DIGITAL	A Fully Digital Front-End Architecture for ECG Acquisition System with 0.5 V Supply		BASEPAPER
IXV40	DSP	Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application		BASEPAPER
IXV41	DSP	Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding		BASEPAPER
IXV42	DSP	A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing		BASEPAPER
IXV43	ARITHMATIC	A New Binary-Halved Clustering Method and ERT Processor for ASSR System		BASEPAPER
IXV44	DSP	The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems		BASEPAPER
IXV45	LOWPOWER	Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals		BASEPAPER
IXV46	ARITHMATIC	Source Code Error Detection in High-Level Synthesis Functional Verification		BASEPAPER
IXV47	NETWORK	In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers		BASEPAPER
IXV48	DIGITAL	OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application		BASEPAPER
IXV49	MEMORY	A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell		BASEPAPER

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Admission to the Ph.D Programme (Full-time and Part-time) in Pilani, Goa and Hyderabad Campuses of BITS Pilani for Second Semester, Academic Year 2024-25 will open shortly.

4 March, 2024 | Pilani

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